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51. 发明申请

US20120317346A1 DATA STORING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME 有权
标题翻译：数据存储方法，以及使用其的存储器控制器和存储器存储装置
公开(公告)号：US20120317346A1
公开(公告)日：2012-12-13
申请号：US13587923
申请日：2012-08-17
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A data storing method for a rewritable non-volatile memory module is provided. The method includes receiving page data to be stored in a first logical address. The method also includes determining whether a storage status of the rewritable non-volatile memory module is a predetermined status; if yes, using a first writing mode to write the page data into the rewritable non-volatile memory module; if no, using a second writing mode to write the page data into the rewritable non-volatile memory module. In the first writing mode, lower physical program units of the rewritable non-volatile memory module are applied for writing data, and upper physical program units of the rewritable non-volatile memory module are not applied for writing data; in the second writing mode, the upper physical program units and the lower physical program units are applied for writing data.
摘要翻译：提供了一种用于可重写非易失性存储器模块的数据存储方法。该方法包括接收要存储在第一逻辑地址中的页面数据。该方法还包括确定可重写非易失性存储器模块的存储状态是否是预定状态; 如果是，使用第一写入模式将页面数据写入可重写非易失性存储器模块; 如果否，则使用第二写入模式将页面数据写入可重写非易失性存储器模块。在第一写入模式中，应用可重写非易失性存储器模块的较低物理程序单元来写入数据，并且不将可重写非易失性存储器模块的较高物理程序单元应用于写入数据; 在第二写入模式中，应用上层物理程序单元和下部物理程序单元来写入数据。

52. 发明申请

US20120278535A1 DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS 有权
标题翻译：数据写入方法，存储器控制器和存储器存储器
公开(公告)号：US20120278535A1
公开(公告)日：2012-11-01
申请号：US13183470
申请日：2011-07-15
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/1435 , G06F11/2094 , G06F2212/1032 , G06F2212/7202 , G06F2212/7209
摘要： A data writing method for writing data belonging to a logical page into a rewritable non-volatile memory module is provided. In the data writing method, a mark count value is set for each logical page. Whether the mark count value corresponding to the logical page is greater than a predetermined threshold is determined If the mark count value corresponding to the logical page is not greater than the predetermined threshold, the mark count value corresponding to the logical page is counted, and the data and the mark count value corresponding to the logical page are written into a first storage area or a second storage area. Otherwise, the data and the mark count value corresponding to the logical page are written into the second storage area. Thereby, data stored in the rewritable non-volatile memory module can be effectively identified and data loss caused by power failure can be avoided.
摘要翻译：提供一种将属于逻辑页面的数据写入可重写非易失性存储器模块的数据写入方法。在数据写入方法中，为每个逻辑页面设置标记计数值。确定与逻辑页对应的标记计数值是否大于预定阈值如果与逻辑页对应的标记计数值不大于预定阈值，则对与逻辑页对应的标记计数值进行计数，对应于逻辑页面的数据和标记计数值被写入第一存储区域或第二存储区域。否则，将对应于逻辑页面的数据和标记计数值写入第二存储区域。从而，可以有效地识别存储在可重写非易失性存储器模块中的数据，并且可以避免由电源故障引起的数据丢失。

53. 发明申请

US20120254511A1 MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND DATA WRITING METHOD 有权
标题翻译：内存存储设备，存储控制器和数据写入方法
公开(公告)号：US20120254511A1
公开(公告)日：2012-10-04
申请号：US13111959
申请日：2011-05-20
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/073 , G06F11/0766 , G06F11/1048 , G06F11/1435 , G06F11/2094 , G06F2212/7201
摘要： A memory storage device, a memory controller, and a data writing method are provided. The memory storage device has a rewritable non-volatile memory chip including a plurality of physical units, and each of the physical units has a plurality of physical pages. The data writing method includes configuring a plurality of logical units to be mapped to a portion of the physical units, and each of the logical unit has a plurality of logical pages. The data writing method also includes receiving a first write data from a host system and writing the first write data into the ith physical page in a substitute physical unit selected from the physical units. The data writing method further includes writing a first address access information corresponding to the first write data and a second address access information into the ith physical page. Herein i is a positive integer.
摘要翻译：提供了存储器存储设备，存储器控制器和数据写入方法。存储器存储装置具有包括多个物理单元的可重写非易失性存储器芯片，并且每个物理单元具有多个物理页面。数据写入方法包括配置要映射到物理单元的一部分的多个逻辑单元，并且每个逻辑单元具有多个逻辑页。数据写入方法还包括从主机系统接收第一写入数据并将第一写入数据写入从物理单元中选择的替代物理单元中的第i个物理页。数据写入方法还包括将与第一写入数据相对应的第一地址访问信息和第二地址访问信息写入第i个物理页面。这里我是一个正整数。

54. 发明授权

US08250286B2 Block management method, and storage system and controller using the same 有权
标题翻译：块管理方法，以及存储系统和控制器的使用方法
公开(公告)号：US08250286B2
公开(公告)日：2012-08-21
申请号：US12259829
申请日：2008-10-28
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonging to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonging to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system.
摘要翻译：提供了一种用于管理多级单元（MLC）NAND闪速存储器的块管理方法，其中MLC NAND闪速存储器具有分组为至少数据区域和备用区域的多个物理块，每个物理块具有被分成多个上部页的多个页面以及其写入速度大于上部页面的多个下部页面。块管理方法包括配置由主机访问的多个逻辑块，记录属于频繁访问块的逻辑块，并执行特殊模式以使用MLC NAND闪速存储器的至少两个物理块的下页用于存储属于经常访问的块的一个逻辑块的数据。因此，可以提高存储系统的访问速度。

55. 发明申请

US20120131263A1 MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR RESPONDING HOST COMMAND 有权
标题翻译：存储器存储器，其存储器控制器以及用于响应主机命令的方法
公开(公告)号：US20120131263A1
公开(公告)日：2012-05-24
申请号：US12976989
申请日：2010-12-22
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： A memory storage device, a memory controller thereof, and a method for responding host commands are provided. The memory storage device has a flash memory chip and a buffer memory. The present method includes receiving a write command issued by a host system and determining whether the write command causes the memory storage device to trigger a data moving procedure. If the write command does not cause the memory storage device to trigger the data moving procedure, the present method further includes sending an acknowledgement message corresponding to the write command to the host system after data corresponding to the write command is completely transferred to the buffer memory.
摘要翻译：提供了存储器存储设备，其存储器控制器以及用于响应主机命令的方法。存储器存储装置具有闪存芯片和缓冲存储器。本方法包括接收由主机系统发出的写入命令，并确定写入命令是否使存储器存储设备触发数据移动过程。如果写入命令不使存储器存储设备触发数据移动过程，则本方法还包括在对应于写入命令的数据被完全传送到缓冲存储器之后，向主机系统发送与写入命令相对应的确认消息。

56. 发明申请

US20120110300A1 DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS 有权
标题翻译：数据管理方法，存储器控制器和存储器存储器
公开(公告)号：US20120110300A1
公开(公告)日：2012-05-03
申请号：US13030147
申请日：2011-02-18
申请人： Chih-Kang Yeh
发明人： Chih-Kang Yeh
IPC分类号： G06F12/06
CPC分类号： G06F12/0246
摘要： A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened.
摘要翻译：提供了数据管理方法，存储器控制器和存储器存储装置。该方法包括将可重写非易失性存储器模块的物理单元分组成至少数据区域和自由区域。该方法还包括配置用于映射到数据区的物理单元的逻辑单元，并将属于逻辑单元的逻辑单元的更新数据有序地写入从空闲区域获得的物理单元的物理页面。该方法还包括配置逻辑页面的根单元，为每个根单元配置入口链，并在入口链上建立条目以记录更新的逻辑页的更新信息，其中每个逻辑页对应于根单元。因此，有效地减少用于存储更新信息的表格大小，有效缩短搜索有效数据的时间。

57. 发明授权

US08001317B2 Data writing method for non-volatile memory and controller using the same 有权
标题翻译：用于非易失性存储器和控制器的数据写入方法
公开(公告)号：US08001317B2
公开(公告)日：2011-08-16
申请号：US12025485
申请日：2008-02-04
申请人： Chih-Kang Yeh , Chien-Hua Chu , Jia-Yi Fu
发明人： Chih-Kang Yeh , Chien-Hua Chu , Jia-Yi Fu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1032 , G06F2212/7203 , G06F2212/7207
摘要： A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
摘要翻译：提供了一种用于非易失性存储器的数据写入方法，其中非易失性存储器包括数据区域和备用区域。在数据写入方法中，分别使用非易失性存储器的替代区域中的多个块来代替数据区域中的多个块，其中写入数据区域中的块的数据被写入到在替代区域中的块，并且替换区域中的块从非易失性存储器的备用区域中选择。非易失性存储器的多个临时块被用作替换区域中的块的临时区域，其中临时区域用于临时存储要写入替换区域中的块的数据。

58. 发明授权

US07975096B2 Storage system having multiple non-volatile memories, and controller and access method thereof 有权
标题翻译：具有多个非易失性存储器的存储系统及其控制器及其访问方法
公开(公告)号：US07975096B2
公开(公告)日：2011-07-05
申请号：US12197468
申请日：2008-08-25
申请人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
发明人： Jiunn-Yeong Yang , Chien-Hua Chu , Kuo-Yi Cheng , Li-Chun Liang , Chih-Kang Yeh
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F2212/2022
摘要： A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.
摘要翻译：提供了包括传输接口，存储器模块和控制器的非易失性存储器存储系统。存储器模块包括第一和第二非易失性存储器芯片。可以通过经由芯片使能引脚从控制器接收芯片使能信号来同时启用第一和第二非易失性存储器芯片。当控制器执行多通道访问时，在使能具有芯片使能信号的第一非易失性存储器芯片和第二非易失性存储器芯片之后，控制器向第一和第二非易失性存储器芯片提供访问指令。当控制器执行单通道访问时，控制器将访问信号提供给第一和第二非易失性存储器芯片中的一个，并且在启用第一非易失性存储器芯片之后，向另一个提供非访问指令，具有芯片使能信号的第二非易失性存储器芯片。

59. 发明申请

US20110154162A1 DATA WRITING METHOD FOR A FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE APPARATUS USING THE SAME 有权
标题翻译：用于闪速存储器的数据写入方法，以及闪存存储器控制器和使用其的闪速存储器存储装置
公开(公告)号：US20110154162A1
公开(公告)日：2011-06-23
申请号：US12705307
申请日：2010-02-12
申请人： Chien-Fu Tseng , Yu-Hung Liu , Li-Chun Liang , Chih-Kang Yeh
发明人： Chien-Fu Tseng , Yu-Hung Liu , Li-Chun Liang , Chih-Kang Yeh
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2707 , G06F11/1068 , H03M13/13
摘要： A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.
摘要翻译：提供了一种用于闪速存储器的数据写入方法，以及使用其的闪速存储器控制器和闪速存储器存储装置。首先，从主机系统接收数据。接下来，数据被分成至少一个帧。之后，生成对应于该帧的错误校验（ECC）代码，以形成至少一个ECC帧。然后，ECC帧被分成多个帧段。最后，根据非顺序的顺序将帧段写入闪存芯片。

60. 发明授权

US07954019B2 Flash storage device and method and system for testing the same 有权
标题翻译： Flash存储设备及其测试方法和系统
公开(公告)号：US07954019B2
公开(公告)日：2011-05-31
申请号：US12369284
申请日：2009-02-11
申请人： Ban-Hui Chen , Chih-Kang Yeh
发明人： Ban-Hui Chen , Chih-Kang Yeh
IPC分类号： G11C29/00 , G11C16/04
CPC分类号： G11C29/48 , G11C16/04 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C2029/0401
摘要： A flash storage device and a testing method and a testing system for the flash storage device are provided. The testing system includes a testing apparatus and the flash storage device. The flash storage device includes a controller, a flash memory module, a plurality of peripheral pins and at least one test pin. The flash storage device receives an enable signal transmitted from the testing apparatus through the test pin. Subsequently, the controller outputs a signal to the testing apparatus through each peripheral pin based to the enable signal. Finally, the testing apparatus verifies the signal outputted by each peripheral pin.
摘要翻译：提供闪存存储装置以及用于闪存存储装置的测试方法和测试系统。测试系统包括测试设备和闪存设备。闪存存储设备包括控制器，闪存模块，多个外设引脚和至少一个测试引脚。闪存存储装置通过测试引脚接收从测试装置发送的使能信号。随后，控制器根据使能信号通过每个外设引脚向测试装置输出一个信号。最后，测试装置验证每个外设引脚输出的信号。

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