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51. 发明授权

US5828891A Multilevel interrupt device 失效
标题翻译：多级中断装置
公开(公告)号：US5828891A
公开(公告)日：1998-10-27
申请号：US766689
申请日：1996-12-13
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
IPC分类号： G06F13/24 , G06F9/48 , G06F13/26 , G06F9/46
CPC分类号： G06F13/26
摘要： The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips. This device (10) is connected to a microprocessor (100) and N peripheral chips (200,210,230) through data/address busses (108,110) and it is also connected to a memory (150) by an additional bus (112). An interrupt operation starts when any one of the peripheral chips activates an interrupt signal through OR gate (220) detected by the microprocessor. The invention avoids to involve the microprocessor in the determination of the interrupt requester except for the generation of a common start.sub.-- address decoded by logic (180) for starting interrupt operations and a common end.sub.-- address decoded by logic (190) for ending it. Owing to the start.sub.-- address and the interrupt signals (173,174) received, latch (170) generates a translated address to memory (150) through a multiplexer (160) to start the corresponding interrupt routine stored at this translated address. The activation of any one of the peripheral chips leads to the reading of the corresponding interrupt routine stored in the memory without requiring any action of the microprocessor. The number of interrupt routines depends on the possible combinations of the N interrupt signals.
摘要翻译：本发明涉及使用公共微处理器中断信号（101）来处理从N个外围芯片接收的中断信号（INT1，...，INTN）的多电平中断装置（10）。该设备（10）通过数据/地址总线（108,110）连接到微处理器（100）和N个外围芯片（200,210,230），并且还通过附加总线（112）连接到存储器（150）。当任何一个外围芯片通过由微处理器检测到的或门（220）激活中断信号时，中断操作开始。本发明避免涉及微处理器确定中断请求者，除了生成由用于启动中断操作的逻辑（180）解码的公共起始地址以及由逻辑（190）解码以用于结束它的公共结束地址。由于接收到起始地址和中断信号（173,174），锁存器（170）通过多路复用器（160）产生到存储器（150）的转换地址，以启动存储在该翻译地址处的相应中断程序。任何一个外围芯片的激活导致读取存储在存储器中的相应的中断程序，而不需要微处理器的任何动作。中断程序的数量取决于N个中断信号的可能组合。

52. 发明授权

US5771262A Impedance adapter for network coupler cable 失效
标题翻译：网络耦合器电缆阻抗适配器
公开(公告)号：US5771262A
公开(公告)日：1998-06-23
申请号：US716077
申请日：1996-09-19
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
IPC分类号： H04L25/02 , H03H11/28 , H04B3/02 , H04B3/00
CPC分类号： H04B3/02 , H03H11/28
摘要： The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109). This circuit (109) determines if the resistors value selected by the magnetic coils of said impedance switching circuit (110) is equal or not equal to the impedance of the network lines (106,105). Thus, it compares VS to a voltage Vref (25) to generate an output which selects and activates the correct magnetic coil for changing or keeping equal the resistors of the receive/transmit impedance network (102,103) currently connected to the network lines (105,106).
摘要翻译：本发明提供一种阻抗适配器，其通过与所连接的发射机/接收机（100,101）串联/并行安装的各种阻抗的受控切换，自动切换到与网络发射/接收线路阻抗（105,106）匹配的阻抗。对于高速适配器，由于高传输速率，需要一个平衡的发射器/接收器来限制串扰效应。发射/接收阻抗适配网络（102-103）由电阻器和继电器触点的串联/并联网络组成，其由阻抗开关电路（110）的磁线圈独立地切换，并且具有与不同的不同网络阻抗匹配的值国家规定。通过使用双偏压电压技术的原理，测量电路（108）检测向上和向下的电压（VA，VB），VB放大2以产生模拟信号VS（VS = VA-2VB）到控制逻辑电路 109）。该电路（109）确定由所述阻抗开关电路（110）的磁线圈选择的电阻值是否等于网线（106,105）的阻抗。因此，它将VS与电压Vref（25）进行比较以产生输出，该输出选择并激活正确的磁线圈，用于改变或保持与当前连接到网络线路（105,106）的接收/发射阻抗网络（102,103）的电阻相等，。

53. 发明授权

US5701468A System for performing data compression based on a Liu-Zempel algorithm 失效
标题翻译：基于Liu-Zempel算法进行数据压缩的系统
公开(公告)号：US5701468A
公开(公告)日：1997-12-23
申请号：US444139
申请日：1995-05-18
申请人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois LePennec
发明人： Alain Benayoun , Jacques Fieschi , Patrick Michel , Jean-Francois LePennec
IPC分类号： G06F5/00 , G06T9/00 , H03M7/30 , H03M7/40 , H03M7/46
CPC分类号： H03M7/3088 , G06T9/005 , Y10S707/99942
摘要： Data compression using a Liv-Zempel algorithm is enhanced by organizing strings of data in a dictionary using a set of related four related fields. The first field contains an index or codeword for the last character of the string currently being processed. The second field contains an index or codeword for a SON string, a string which includes all of the characters of the current string plus one additional character. The third field contains an index or codeword for a BROTHER string which is identical to the current string except that the last characters in the two strings differ. The fourth field contains an index or codeword for a PARENT to the current string. The PARENT includes all of the characters of the current string except the last character. The memory arrangement comprises a tree structure which can be efficiently accessed by a disclosed processor to perform data compression using minimal processing resources.
摘要翻译：使用Liv-Zempel算法的数据压缩通过使用一组相关的四个相关字段组织字典中的数据串来增强。第一个字段包含当前正在处理的字符串的最后一个字符的索引或代码字。第二个字段包含SON字符串的索引或代码字，一个包含当前字符串的所有字符加上一个附加字符的字符串。第三个字段包含与当前字符串相同的BROTHER字符串的索引或代码字，但两个字符串中的最后一个字符不同。第四个字段包含用于当前字符串的PARENT的索引或代码字。 PARENT包括除最后一个字符之外的当前字符串的所有字符。存储器装置包括树结构，其可以被公开的处理器有效地访问以使用最少的处理资源执行数据压缩。

54. 发明授权

US07383311B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US07383311B2
公开(公告)日：2008-06-03
申请号：US11322378
申请日：2006-01-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

55. 发明授权

US07304941B2 Switchover system and method in a data packet switching network 有权
标题翻译：数据分组交换网络中的切换系统和方法
公开(公告)号：US07304941B2
公开(公告)日：2007-12-04
申请号：US10412953
申请日：2003-04-11
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： H04J3/14 , H04L12/28
CPC分类号： H04L49/552 , H04L49/1523
摘要： A switchover system and method is described. The invention preferably operates in a data packet switching system for transmitting through a switching arrangement data packets that comprise at least a data packet identifier. The switching arrangement comprises at least an active switch card associated to a backup switch card. And the active switch card and the backup switch card receive simultaneously at least a data packet and transmit it to a network adapter device. The switchover system comprises active and backup means for respectively storing at an active and backup data packet address the transmitted at least data packet. It also comprises switchover detecting means coupled to the active and backup storing means for detecting a switchover event, and control means coupled to the active and backup storing means and to the switchover detecting means for setting the backup storing means when a switchover event is detected.
摘要翻译：描述了切换系统和方法。本发明优选地在数据分组交换系统中操作，用于通过交换机构传送至少包括数据分组标识符的数据分组。交换装置至少包括与备用交换机卡相关联的活动交换卡。并且主动交换机卡和备用交换机卡至少同时接收数据包并将其发送到网络适配器设备。切换系统包括主动和备用装置，用于分别在活动和备份数据分组地址存储发送的至少数据分组。还包括耦合到用于检测切换事件的主动和备份存储装置的切换检测装置，以及耦合到主动和备份存储装置的控制装置和用于在检测到切换事件时设置备份存储装置的切换检测装置。

56. 发明授权

US07240301B2 System and method to insert new pages with a schematic capture tool 失效
标题翻译：使用原理图捕获工具插入新页面的系统和方法
公开(公告)号：US07240301B2
公开(公告)日：2007-07-03
申请号：US10904310
申请日：2004-11-03
申请人： Alain Benayoun , Jean Louis Grillo
发明人： Alain Benayoun , Jean Louis Grillo
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G06F17/248
摘要： A computer implemented method to perform an insertion request of new schematic pages within a plurality of numbered schematic pages created with a design schematic capture tool is described. The method allows a user to insert as much as new pages in a user friendly manner by being implemented in a design schematic capture tool through a Graphical User Interface (GUI). The GUI offers a location field to enter the schematic page number where to insert the new pages, a number field to enter the number of new schematic pages to be inserted, and an execution key to be depressed to execute the insertion operation automatically.
摘要翻译：描述了使用设计示意图捕获工具创建的在多个编号的示意图页内执行新原理图页的插入请求的计算机实现的方法。该方法允许用户通过在图形用户界面（GUI）中在设计原理图捕获工具中实现，以用户友好的方式插入新页面。 GUI提供了一个位置字段，用于输入插入新页面的原理图页码，输入要插入的新原理图页面数量的数字字段，以及要按下的执行键以自动执行插入操作。

57. 发明授权

US07142515B2 Expandable self-route multi-memory packet switch with a configurable multicast mechanism 失效
标题翻译：具有可配置多播机制的可扩展自路由多内存分组交换机
公开(公告)号：US07142515B2
公开(公告)日：2006-11-28
申请号：US10043028
申请日：2002-01-09
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： G06F13/36
CPC分类号： H04L49/1507 , H04L49/201 , H04L49/45 , H04L49/505
摘要： Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block at each crosspoint of the switch module including memory control means for determining from the header of the received data packet whether the packet is to be forwarded to the output port associated with the crosspoint and a data memory unit for storing at least the data packet into the data memory unit before sending it to the output port. The memory control means analyzes all the bytes following the header when it includes a specific configuration indicating that the packet is a multicast address packet preceding a multicast frame in order to determine whether the packets of the multicast frame are to be forwarded to the output port.
摘要翻译：数据传输系统包括由集线器（12）互连的多个局域网（LAN）（10-1至10-4），所述集线器包括分别连接到所述LAN的同一多个LAN适配器（16-1至16-4）以及分组交换机（14），至少包括互连所有LAN适配器的分组交换模块，其中由任何适配器发送到分组交换机的分组包括至少包含分组所转发到的适配器的地址的报头。该系统包括在交换机模块的每个交叉点处的存储器块，包括存储器控制装置，用于根据接收到的数据包的头部确定要将数据包转发到与交叉点相关联的输出端口，以及数据存储单元，用于存储在在将数据包发送到输出端口之前，将数据包送入数据存储单元。当存储器控制装置包括指示分组是组播帧之前的多播地址分组的特定配置以便确定多播帧的分组是否被转发到输出端口时，分析报头之后的所有字节。

58. 发明申请

US20060098026A1 System and Method to Insert New Pages with a Schematic Capture Tool 失效
标题翻译：用原理图捕获工具插入新页面的系统和方法
公开(公告)号：US20060098026A1
公开(公告)日：2006-05-11
申请号：US10904310
申请日：2004-11-03
申请人： Alain Benayoun , Jean Grillo
发明人： Alain Benayoun , Jean Grillo
IPC分类号： G09G5/00
CPC分类号： G06F17/248
摘要： A computer implemented method to perform an insertion request of new schematic pages within a plurality of numbered schematic pages created with a design schematic capture tool is described. The method allows a user to insert as much as new pages in a user friendly manner by being implemented in a design schematic capture tool through a Graphical User Interface (GUI). The GUI offers a location field to enter the schematic page number where to insert the new pages, a number field to enter the number of new schematic pages to be inserted, and an execution key to be depressed to execute the insertion operation automatically.
摘要翻译：描述了使用设计示意图捕获工具创建的在多个编号的示意图页内执行新原理图页的插入请求的计算机实现的方法。该方法允许用户通过在图形用户界面（GUI）中在设计原理图捕获工具中实现，以用户友好的方式插入新页面。 GUI提供了一个位置字段，用于输入插入新页面的原理图页码，输入要插入的新原理图页面数量的数字字段，以及要按下的执行键以自动执行插入操作。

59. 发明授权

US06996111B1 ATM node having local error correcting procedures 失效
标题翻译： ATM节点具有本地纠错程序
公开(公告)号：US06996111B1
公开(公告)日：2006-02-07
申请号：US09991000
申请日：2001-11-14
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
IPC分类号： H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5652
摘要： A node for a telecommunications network has a segmentation and reassembly module (SAR module) to perform segmentation and reassembly (SAR) on cells received by the node, the SAR module particularly providing Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation (referred to as VCI/VPI translation), and has a direct memory access (DMA) mechanism for a storage external to the SAR module, the SAR module performing a first DMA access when the VCI/VPI translation are representative of an error code correcting (ECC) procedure to be carried out in the node, and the SAR module performing a second DMA access when the VCI/VPI translation corresponds to a message that does not require a local ECC procedure. A coder/decoder module performs an ECC procedure on the cells. A controller controls the coder/decoder module to perform an error correcting procedure in response to the detection of the first DMA access. The first DMA access uses a first address and the second DMA uses a second address. A Reed-Solomon coder-decoder or a Hamming coder-decoder may be used to perform the ECC procedure. An address decoder interprets the VCI/VPI identifiers to control whether or not an ECC procedure is done.
摘要翻译：用于电信网络的节点具有分段和重组模块（SAR模块），用于对由节点接收的小区执行分段和重组（SAR），SAR模块特别提供虚拟信道标识符（VCI）和虚拟路径标识符（VPI）转换（称为VCI / VPI转换），并且具有用于SAR模块外部的存储器的直接存储器访问（DMA）机制，当VCI / VPI转换代表纠错码时，SAR模块执行第一DMA访问（ECC）过程，并且当VCI / VPI转换对应于不需要本地ECC过程的消息时，SAR模块执行第二DMA访问。编码器/解码器模块对单元执行ECC过程。控制器控制编码器/解码器模块响应于第一DMA访问的检测来执行纠错过程。第一个DMA访问使用第一个地址，第二个DMA使用第二个地址。可以使用里德 - 所罗门编码器解码器或汉明编码器解码器来执行ECC过程。地址解码器解释VCI / VPI标识符以控制ECC过程是否完成。

60. 发明授权

US06968386B1 System for transferring data files between a user workstation and web server 失效
标题翻译：用于在用户工作站和Web服务器之间传输数据文件的系统
公开(公告)号：US06968386B1
公开(公告)日：2005-11-22
申请号：US09660043
申请日：2000-09-12
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
IPC分类号： G06F13/12 , G06F15/167 , G06F15/16 , H04B1/38 , H04L5/16
CPC分类号： G06F13/128
摘要： System for transferring a data file from a web server to a user workstation through a network and reciprocally, the user workstation including a hard disk (205) for storing the data file being transferred over a SCSI bus (208). The user workstation includes a dual-port memory (304) for storing temporarily the data file, a network logic unit (302) interconnected between the network and the input port of the dual-port memory for receiving the data file from the network and transmitting it to the dual-port memory, and a SCSI logic unit (303) interconnected between the output port of the dual-port memory and the SCSI bus for transferring the data file from the dual-port memory to the hard disk over the SCSI bus and reciprocally.
摘要翻译：用于通过网络将数据文件从网络服务器传送到用户工作站的系统，所述用户工作站包括用于存储通过SCSI总线（208）传送的数据文件的硬盘（205）。用户工作站包括用于临时存储数据文件的双端口存储器（304），在网络与双端口存储器的输入端口之间互连的网络逻辑单元（302），用于从网络接收数据文件并发送双端口存储器和在双端口存储器的输出端口和SCSI总线之间互连的SCSI逻辑单元（303），用于通过SCSI总线将数据文件从双端口存储器传送到硬盘并相互地。

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