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51. 发明申请

WO2017168119A1 CORRELATED ELECTRON RESISITVE MEMORY ELEMENT AS CONNECTING ELEMENT BETWEEN LOGIC CIRCUITS 审中-公开
标题翻译：相关电子阻抗存储器元件作为逻辑电路之间的连接元件
公开(公告)号：WO2017168119A1
公开(公告)日：2017-10-05
申请号：PCT/GB2017/050505
申请日：2017-02-24
申请人： ARM LTD
发明人： CHANDRA, Vikas , AITKEN, Robert Campbell
IPC分类号： G11C13/00 , H03K19/177
CPC分类号： H03K19/1776 , G11C13/0007 , G11C13/0069 , H03K19/17704 , H03K19/17736 , H03K19/17744 , H03K19/1778
摘要： According to one embodiment of the present disclosure, a circuit is provided. The circuit includes a first logic circuit, a second logic circuit, and a Correlated Electron Switch, herein after termed CES, element. The CES element is configured to enable or disable a connection between the first logic circuit and the second logic circuit.
摘要翻译：根据本公开的一个实施例，提供了一种电路。该电路包括第一逻辑电路，第二逻辑电路和相关电子开关，在下文中称为CES元件。 CES元件被配置为启用或禁用第一逻辑电路和第二逻辑电路之间的连接。

52. 发明申请

WO2017158344A1 A PIEZOELECTRIC THIN FILM ELEMENT 审中-公开
标题翻译：压电薄膜元件
公开(公告)号：WO2017158344A1
公开(公告)日：2017-09-21
申请号：PCT/GB2017/050695
申请日：2017-03-14
申请人： XAAR TECHNOLOGY LIMITED
发明人： MARDILOVICH, Peter , KO, Song-Won , TROLIER-MCKINSTRY, Susan , BORMAN, Trent , ZHU, Wanlin
IPC分类号： H01L41/187 , H01L41/318
摘要： A method for the manufacture of a piezoelectric thin film element comprising a first electrode,a second electrode and one or more piezoelectric thin films there between which method comprises forming a piezoelectric thin film comprising PZT by a chemical solution deposition using three solutions wherein the forming of the PZT thin film comprises forming a bulk PZT thin film layer from the three solutions, wherein each solution has a Zr/Ti content which is different from that of any other solution and at least one solution has an excess lead content greater than that of any other solution, such that the bulk PZT thin film layer has a substantially uniform lead content and Zr/(Zr+Ti) ratio in its thickness direction.
摘要翻译：一种用于制造压电薄膜元件的方法，所述压电薄膜元件包括第一电极，第二电极和一个或多个压电薄膜，在所述压电薄膜元件之间包括通过化学溶液形成包含PZT的压电薄膜使用三种溶液进行沉积，其中形成PZT薄膜包括由三种溶液形成块体PZT薄膜层，其中每种溶液具有不同于任何其他溶液的Zr / Ti含量，并且至少一种溶液具有过量的铅含量大于任何其它溶液的铅含量，使得体PZT薄膜层在其厚度方向上具有基本均匀的铅含量和Zr /（Zr + Ti）比率。

53. 发明申请

WO2017129933A1 DROPLET DEPOSITION HEAD 审中-公开
标题翻译：滴落沉积头
公开(公告)号：WO2017129933A1
公开(公告)日：2017-08-03
申请号：PCT/GB2016/054036
申请日：2016-12-22
申请人： XAAR TECHNOLOGY LIMITED
发明人： KO, Song-Won , MARDILOVICH, Peter , TATUM, John Philip , CAZACU, Alexandru
IPC分类号： B41J2/045 , B41J2/16 , B41J2/14
CPC分类号： B41J2/04573 , B41J2/14209 , B41J2/1609 , B41J2/164 , B41J2/1642 , B41J2002/14225
摘要： A droplet deposition head having a fluid chamber connected to a droplet ejection nozzle and to a reservoir for the fluid, and a piezoelectric actuator element formed at least in part by a fluid chamber wall having an electrode thereon, which element is displaceable in response to a drive voltage to generate a pressure in the chamber to eject a droplet of fluid from the chamber through the nozzle wherein the electrode is provided with a passivation coating which comprises, at least in part, a laminate comprising an inorganic insulating layer nearest to or contacting the electrode and an organic insulating layer overlying the inorganic insulating layer wherein defects in the insulating layers tend to be misaligned at the interface there between and wherein the inorganic insulating layer has thickness less than or equal to 500 nm and the organic insulating layer has a thickness less than 3 μιη.
摘要翻译：液滴沉积头具有连接到液滴喷嘴和用于流体的贮存器的流体室以及至少部分地由其上具有电极的流体室壁形成的压电致动器元件，该元件响应于驱动电压而可移位以在腔室中产生压力以通过喷嘴从腔室喷射流体液滴，其中该电极设置有钝化涂层，该钝化涂层至少部分地包括层压体，该层压体包括与所述电极最接近或接触的无机绝缘层和覆盖所述无机绝缘层的有机绝缘层，其中所述绝缘层中的缺陷往往在它们之间的界面处未对准，并且其中所述无机绝缘层具有小于或等于500nm的厚度，以及有机绝缘层具有小于3μm的厚度。

54. 发明申请

WO2017121999A1 A PRINTHEAD CIRCUIT 审中-公开
标题翻译：一个PRINTHEAD电路
公开(公告)号：WO2017121999A1
公开(公告)日：2017-07-20
申请号：PCT/GB2017/050050
申请日：2017-01-10
申请人： XAAR TECHNOLOGY LIMITED
发明人： VAN BROCKLIN, Andrew L. , JEAPES, Stephen , HURST, Ian Anthony
IPC分类号： B41J2/045
CPC分类号： B41J2/04581 , B41J2/04541 , B41J2/0455 , B41J2/04588
摘要： A print head circuit for providing pulses for driving two or more actuating elements, the circuit comprising a cold switch drive circuit, for driving an actuating element for a first phase of a first pulse, the cold switch drive circuit having a cold drive switch for selectively coupling a drive waveform to the actuating element during the first phase according to a print signal; and a hot switch drive circuit, for driving the actuating element for a second phase of the first pulse, wherein the hot switch drive circuit is configured to drive the actuating element during the second phase according to an actuating element compensation indication signal.
摘要翻译：用于提供用于驱动两个或更多个致动元件的脉冲的打印头电路，所述电路包括冷开关驱动电路，用于驱动用于第一脉冲的第一相的致动元件，所述冷开关驱动器电路，具有根据打印信号在第一阶段期间选择性地将驱动波形耦合到致动元件的冷驱动开关; 以及用于驱动用于第一脉冲的第二相的致动元件的热开关驱动电路，其中热开关驱动电路被配置为根据致动元件补偿指示信号在第二阶段期间驱动致动元件。 >

55. 发明申请

WO2017109460A1 CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY 审中-公开
标题翻译：可配置阻抗阵列的电路和方法
公开(公告)号：WO2017109460A1
公开(公告)日：2017-06-29
申请号：PCT/GB2016/053931
申请日：2016-12-14
申请人： ARM LTD
发明人： BHAVNAGARWALA, Azeez Jennudin , CHANDRA, Vikas , CLINE, Brian Tracy
IPC分类号： G11C13/00 , H03M1/78 , H03M1/80
CPC分类号： G11C13/0069 , G11C11/38 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C17/12 , G11C2213/75 , H03M1/00 , H03M1/78 , H03M1/808
摘要： A configurable impeder is provided. The configurable impeder comprises multiple Correlated Electron Switches(CESs). Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CESfrom the plurality of CESs.
摘要翻译：
提供了一个可配置的阻抗器。可配置的阻抗器包括多个相关电子开关（CES）。每个CES能够被配置成多个阻抗状态之一。此外，提供编程电路。编程电路根据输入信号提供多个编程信号。每个编程信号配置来自多个CES的相应CES的阻抗状态。

56. 发明申请

WO2017098209A1 RESISTIVE CROSS-POINT STORAGE ARRAY 审中-公开
标题翻译：有吸引力的交叉点存储阵列
公开(公告)号：WO2017098209A1
公开(公告)日：2017-06-15
申请号：PCT/GB2016/053743
申请日：2016-11-29
申请人： ARM LTD
发明人： DAS, Shidhartha , MYERS, James Edward , TOH, Seng
IPC分类号： G11C7/06 , G11C13/00
CPC分类号： G11C13/0007 , G11C7/067 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2213/77
摘要： A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.
摘要翻译：包括存储阵列的设备，所述存储阵列包括第一信号线和第二信号线，与所述第一信号线和所述第二信号线电通信的至少一个相关电子开关，以及控制电路，用于用至少一个编程信号驱动相关电子开关。

57. 发明申请

WO2017085463A1 ZERO LATENCY GATEWAY 审中-公开
标题翻译：零延迟网关
公开(公告)号：WO2017085463A1
公开(公告)日：2017-05-26
申请号：PCT/GB2016/053494
申请日：2016-11-08
申请人： ARM IP LIMITED
发明人： MERIAC, Milosch
IPC分类号： H04L29/06 , H04W4/00
CPC分类号： H04L63/0227 , H04L63/1441 , H04W4/00 , H04W4/70 , H04W4/80
摘要： Broadly speaking, embodiments of the present technique provide apparatus, systems and methods to enable secure communication between devices. In particular, the present techniques provide an apparatus configured to monitor for a data packet transmitted between a transmitter and a receiver, determine if the data packet is permitted to be transmitted, and act on at least part of the data packet to prevent the receiver from acting on the data packet if it is not permitted to be transmitted. In other words, the present techniques provide / implement security filters in a communication channel between a transmitter and a receiver to reduce the risk that unauthorised data packets are sent to, and implemented by, the receiver device.
摘要翻译：概括地说，本技术的实施例提供了用于实现设备之间的安全通信的装置，系统和方法。特别地，本技术提供了一种设备，其被配置为监视在发射机和接收机之间发送的数据分组，确定是否允许发送数据分组，并且对至少部分数据分组起作用以防止接收机从如果数据包不允许传输，则作用于数据包。换句话说，本技术在发射机和接收机之间的通信信道中提供/实施安全滤波器，以降低将未授权数据分组发送到接收机设备并由接收机设备实施的风险。

58. 发明申请

WO2017060687A1 CIRCUIT AND METHOD FOR MONITORING CORRELATED ELECTRON SWITCHES 审中-公开
标题翻译：用于监测相关电子开关的电路和方法
公开(公告)号：WO2017060687A1
公开(公告)日：2017-04-13
申请号：PCT/GB2016/053082
申请日：2016-10-04
申请人： ARM LTD
发明人： SANDHU, Bal S. , AITKEN, Robert , LATTIMORE, George
IPC分类号： G11C13/00 , G11C29/02
CPC分类号： H03K17/687 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0045 , G11C2013/0054 , G11C2029/0409
摘要： A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provides an output signal dependent on the determined impedance state of the CES element.
摘要翻译：提供了一种用于CES元件的监视电路。电路包括控制电路和输出电路。控制电路被配置为改变提供给CES元件的控制信号。可以改变控制信号以确定CES元件的阻抗状态。输出电路提供取决于所确定的CES元件的阻抗状态的输出信号。

59. 发明申请

WO2017055833A1 STANDARD CELL ARCHITECTURE LAYOUT 审中-公开
标题翻译：标准细胞结构布局
公开(公告)号：WO2017055833A1
公开(公告)日：2017-04-06
申请号：PCT/GB2016/053006
申请日：2016-09-28
申请人： ARM LTD
发明人： CASSARD, Alexis
IPC分类号： G06F17/50 , G06F3/0486 , H01L27/02 , G06F3/0481
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Various implementations described herein are directed to providing standard cell architecture layout design. A request to activate a grid is received. A request to place at least one edge of a shape at a particular location on the grid is received from an input device. The at least one edge of the shape is automatically placed in an allowed location based on pre-defined rules.
摘要翻译：本文描述的各种实施方式涉及提供标准小区体系结构布局设计。接收到激活网格的请求。从输入设备接收到将格子的至少一个边缘放置在网格上的特定位置的请求。基于预定义的规则，形状的至少一个边缘自动放置在允许的位置。

60. 发明申请

WO2017042565A1 CONTACT RESISTANCE MITIGATION 审中-公开
标题翻译：接触电阻缓解
公开(公告)号：WO2017042565A1
公开(公告)日：2017-03-16
申请号：PCT/GB2016/052775
申请日：2016-09-08
申请人： ARM LTD
发明人： YERIC, Gregory Munson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5036 , G06F2217/12 , G06F2217/78 , G06F2217/84 , Y02P90/265
摘要： Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.
摘要翻译：本文描述的各种实现涉及用于减轻接触电阻的系统和方法。在一个实现中，方法可以包括分析集成电路的单元的操作条件。该方法可以包括沿着集成电路的关键路径选择性地标记具有定时劣化的小区的实例。该方法可以包括降低具有定时劣化的小区的选择性标记的实例的接触电阻。

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