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51. 发明公开

EP1521187A1 Method and device for configuration of PLDS 审中-公开
标题翻译： Verfahren und Einrichtung zur Konfiguration von PLD
公开(公告)号：EP1521187A1
公开(公告)日：2005-04-06
申请号：EP04104798.6
申请日：2004-09-30
申请人： STMicroelectronics Pvt. Ltd
发明人： Goel, Ashish Kumar , Aggarwal, Davinder
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17748 , G06F17/5054 , H03K19/1776
摘要： The present invention relates to a Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising: an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.
摘要翻译：本发明涉及一种可编程逻辑器件，其为配置存储器编程提供有效的可扩展性，同时需要减少实现的面积，其包括：配置存储器单元的阵列，连接到配置存储器阵列的垂直线的垂直移位寄存器（VSR）单元，连接到配置存储单元阵列的水平线的选择寄存器（SR），提供对选择寄存器（SR）的使能输入的水平移位寄存器（HSR）以及同步的配置状态机（CSM） VSR，SR和HSR的操作。

52. 发明公开

EP1259079A3 "An efficient low power motion estimation of a video frame sequence" 有权
标题翻译：对于视频帧序列高效的低功率的运动估计
公开(公告)号：EP1259079A3
公开(公告)日：2004-12-01
申请号：EP02008699.7
申请日：2002-04-18
申请人： STMicroelectronics Pvt. Ltd
发明人： Chelladurai, Paul, Sathya , Ahmed, Arshad , Nandy, Soumitra, Kumar
IPC分类号： H04N7/26
CPC分类号： H04N19/53 , H04N19/14 , H04N19/194 , H04N19/61
摘要： The present invention provides a system, method and computer program product for efficient low power motion estimation of a digital video image wherein processing requirements are reduced, the reduction being dependent on the content being processed. The method performs motion estimation of a current video image using a search window of previous video image. The method comprises as a first step the formation of the mean pyramids of the reference macroblock and the search area. This is followed by full search at the lowest resolution. The number of CMVs propagated to lower levels is dependent on the QADE of the current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. The process of training over a sequence is triggered at the beginning of every sequence. This training technique is required to determine the value of the maximum distortion band for all QADEs of the macroblocks, occurring over the training frames.

53. 发明公开

EP1473644A2 A method for mapping a logic circuit to a programmable look up table 审中-公开
标题翻译：用于逻辑Schlatkreises映射到一个可编程查找表的方法
公开(公告)号：EP1473644A2
公开(公告)日：2004-11-03
申请号：EP04009701.6
申请日：2004-04-23
申请人： STMicroelectronics Pvt. Ltd
发明人： Sharma, Sunil Kumar , Tomar, Ajay , Samanta, Dhabalendu
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： The present invention provides an improved method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements comprising steps of, forming logic element groups including individual logic elements and/ or previously formed logic element groups that are capable of being accommodative with in the fanin and /or fanout capacity of a target LUT, mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner that at each stage only the unapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.
摘要翻译：对本发明的改进的方法提供了用于映射的逻辑电路，其包含的步骤可互相连接，可编程查找表（LUT）的元素的复数，形成逻辑元件组包括个别逻辑元件和/或先前形成的逻辑元件组也能够为调节与所述扇入和/或所形成的逻辑元件群映射到所述目标LUT，并重复该过程以形成逻辑元件组和映射到目标的LUT用于以这样的方式在整个网络中的目标LUT的扇出能力做在每个阶段仅unapped逻辑元件/元件和前级的映射逻辑元件组被认为是映射。

54. 发明公开

EP1298320A3 Capacitor discharge ignition (CDI) system 审中-公开
标题翻译：电容放电点火系统
公开(公告)号：EP1298320A3
公开(公告)日：2004-10-20
申请号：EP02021534.9
申请日：2002-09-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Dutt, Saibal , Dasgupta, Nabarun , Kulshrestha, Nikhil
IPC分类号： F02P3/08
CPC分类号： F02P15/10 , F02D2041/2075 , F02P3/0846 , F02P3/0884
摘要： This invention relates to an improved Capacitor Discharge Ignition (CDI) system capable of generating intense continuous electrical discharge at spark gap for any desired duration, characterized in that it includes a second controllable power switching means with its input terminal connected to the output terminal of said high voltage d.c. source means, its output terminal connected to the input terminal of said first power switching means, and its control terminal connected to a second output of said control means, the arrangement being such that said first controllable power switching means is used for discharging said discharge capacitor and said second controllable power switching means causes charging of said discharge capacitor, thereby enabling an ignition current through said ignition coil for any desired number of cycles during both the charge and discharge cycles of said discharge capacitor.

55. 发明公开

EP1460640A2 A content addressable memory (CAM) architecture providing improved speed 审中-公开
标题翻译： Architektur eines Inhaltsadressierbaren Speichers mit verbesserter Geschwindigkeit
公开(公告)号：EP1460640A2
公开(公告)日：2004-09-22
申请号：EP04006654.0
申请日：2004-03-19
申请人： STMicroelectronics Pvt. Ltd
发明人： Srivastavaan, Rajeev , Grover, Chiranjeev
IPC分类号： G11C15/04
CPC分类号： G11C15/00
摘要： This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.
摘要翻译：本发明提供了一种内容寻址存储器（CAM）架构，其通过在时钟周期的第一状态中执行互斥操作并且依赖于至少一个先前的操作在相同的第二状态中执行至少一个操作来提供改进的速度时钟周期。内容可寻址存储器（CAM）架构（300）包括连接到比较数据写驱动器（302）和读/写块（305）的CAM单元阵列（303），用于接收比较数据并且分别用于在CAM单元阵列中读取和/或写入数据，所述阵列（303）的所述CAM单元的输出耦合到匹配块（304），提供匹配输出信号线，其标识匹配/ 在搜索操作结束时的不匹配，以及用于在第一状态下实现搜索和地址解码操作以及在匹配的情况下在相同时钟周期的第二状态内启用读或写操作的控制逻辑。

56. 发明公开

EP1447752A2 Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication 审中-公开
标题翻译：方法和系统，用于多处理器的FFT / IFFT计算以最小的处理器间通信
公开(公告)号：EP1447752A2
公开(公告)日：2004-08-18
申请号：EP04100617.2
申请日：2004-02-16
申请人： STMicroelectronics Pvt. Ltd
发明人： Saha, Kaushik , Narayan, Srijib
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.
摘要翻译：本发明提供一个可扩展的方法，用于在多处理器体系结构实现FFT / IFFT计算确实由第一“日志2 P”阶段的计算后消除了对处理器间通信的需要提供改进的吞吐量在实施使用“P”的处理元件，包括同时计算在任一单个处理器或每个“P”处理器的第一“日志2 P”阶段，每个阶段蝴蝶和分发寻求做各链中的“P”的处理器之间的所有后续阶段中的蝴蝶的计算的级联蝴蝶由...组成这些蝴蝶thathave连接在一起的输入和输出，通过相同的处理器处理。因此本发明提供一种系统，用于在多处理器体系结构获得可扩展的实施FFT / IFFT计算的那样通过在实施使用“P”消除了对处理器间通信的需要的第一个“登录2 P”阶段的计算后提供改进的吞吐量处理元件。

57. 发明公开

EP1432126A2 High performance interconnect architecture for FPGAs 审中-公开
标题翻译： LeistungsfähigeVerbindungsarchitekturfürnutzerprogrammierbare Gatterfelder
公开(公告)号：EP1432126A2
公开(公告)日：2004-06-23
申请号：EP03104727.7
申请日：2003-12-16
申请人： STMicroelectronics Pvt. Ltd.
发明人： BAL, Ankur , KHANNA, Namerita
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.
摘要翻译：描述了一种高性能互连架构，其提供减少的延迟最小化电迁移和FPGA中的减小的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。每组相互连接的逻辑块通过互连段链接，所述互连段通过互连层穿过中间逻辑块以直线布线，并且通过连接段选择性地连接到逻辑块。

58. 发明公开

EP1416373A2 Method and apparatus to reduce access time in synchronous fifos with zero latency overhead 审中-公开
标题翻译： Verfahren und Vorrichtung zur Reduzierung der Zugriffszeit同步FIFOs ohen Latenzkosten
公开(公告)号：EP1416373A2
公开(公告)日：2004-05-06
申请号：EP03024591.4
申请日：2003-10-28
申请人： STMicroelectronics Pvt. Ltd
发明人： Chakravarthy, Kalyana , Verma, Jayesh
IPC分类号： G06F7/06
CPC分类号： G06F5/10
摘要： The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.
摘要翻译：连接到先进先出（FIFO）存储器（301）的数据输出端的读取数据选择器（303）从奇数和偶数读指针发生器（304,305）接收选择输入。耦合到选择器的输出端的复用器（306）选择选择器的输出作为FIFO的最终输出。状态控制器（310）控制对最终输出的选择并输入到选择器。还包括以下独立权利要求：（1）减少FIFO缓冲存取时间的方法; 和（2）提供FIFO缓冲器的方法。

59. 发明公开

EP1320048A3 Rapid partial configuration of reconfigurable devices 审中-公开
标题翻译：可重构器件的快速电源配置
公开(公告)号：EP1320048A3
公开(公告)日：2004-03-03
申请号：EP02027923.8
申请日：2002-12-13
申请人： STMicroelectronics Pvt. Ltd
发明人： Goel, AshishKumar , Agarwal, Manish
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： A system and method for enabling rapid partial configuration of reconfigurable devices, wherein configuration definition means define partial configuration requirements, and contain at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. Configuration loading means (300, 310, 320) provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements.

60. 发明公开

EP1330033A2 Utilization of unused IO block for core logic functions 有权
标题翻译：使用不必要的输入/输出块为中心的逻辑功能
公开(公告)号：EP1330033A2
公开(公告)日：2003-07-23
申请号：EP03000105.1
申请日：2003-01-02
申请人： STMicroelectronics Pvt. Ltd
发明人： Chauhan, Rajat , Kaushik, Rajesh
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/17744
摘要： This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.
摘要翻译：本发明提供一种方法和改善的FPGA装置用于使得未使用的触发器或在IO单元和未使用的解码器或在查找表（LUT），用于核心逻辑功能的其它电路元件的其它电路元件的选择性地部署，包括断开装置选择性地断开所述IO垫的电路或从所述LUT电路未使用的电路元件和连接装置，用于所述断开电路元件选择性地连接到要么核心逻辑的连接基质或在它们之间，以提供unabhängig配置的功能。

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