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41. 发明专利

GB2233865A AN ADAPTIVE DETECTION METHOD FOR QUANTIZED SIGNALS 未知
公开(公告)号：GB2233865A
公开(公告)日：1991-01-16
申请号：GB9018361
申请日：1990-08-20
申请人： NOKIA OY AB
发明人： KOHONEN TEUVO
IPC分类号： H04L25/02 , H03M7/34 , H04L25/03 , H04L25/49 , H04L27/00
摘要： The invention is generally concerned with an adaptive detection method for quantized signals having nominal values which at different moments define a finite set of discrete states, wherein the discrete state of a signal at a certain moment is interpreted by comparing the sample value of the signal to a set of reference numbers, on the basis of which the recognition of the signal state takes place. According to the principle of the method the values of the reference numbers used in the detection are corrected adaptively towards the actual signal states of the signal to be detected by, e.g., a k-means clustering method or by self-organizing feature maps.

42. 发明专利

FR2575351B1 未知
公开(公告)号：FR2575351B1
公开(公告)日：1988-05-13
申请号：FR8419646
申请日：1984-12-21
申请人： THOMSON CSF
发明人： FERRE ALAIN , VILLALON YANNICK
IPC分类号： H04N7/30 , G06T1/00 , G06T9/00 , H03M7/30 , H03M7/34 , H04N7/50 , H04N7/12
摘要： This process uses a bidirectional transformation by blocks for images representing highly animated scenes and also uses a differential coding of the transformation coefficients when the pictures show slightly animated scenes. The coding device mainly comprises a cosine transformation device, a subtractor, and inter-image decoding device, a multiplexer, a device for discriminating the blocks showing highly animated scenes and blocks showing slightly animated scenes. The latter device controls the multiplexer. The subtractor and the decoding device make it possible to calculate the difference between each transformation coefficient and the homologous coefficient of the homologous block in the preceding picture. Moreover, a weighting device makes it possible to transmit with a larger number of bits the coefficients or coefficient differences corresponding to the low spatial frequencies of the images.

43. 发明专利

AU530585B2 DELTA MODULATION COMPANDER 未知
公开(公告)号：AU530585B2
公开(公告)日：1983-07-21
申请号：AU6321380
申请日：1980-10-13
申请人： IBM
发明人： CROUSE WILLIAM G
IPC分类号： H03M3/02 , H03M7/34 , H04B14/06 , H03K13/22 , H04B12/04
摘要： Delay circuits (21) and (22) and logic gates (23, 24, 25) provide an output which is representative of three successive like bits appearing on the compander input line. Multiplier (26) multiplies the current delta step value DELTA by /16 and multiplier (27) multiplies the same by - /64. When the output of logic gate (25) is a 1, (three like bits), AND gate (28) let the output of multiplier (26) apply to three input adder (31). The output of this adder then delivers a delta step signal When the output of logic gate (25) is a zero, the new delta step is since AND gate (28) does not deliver any output. Multipliers (26) and (27) are shift registers, and the division by 16 or 64 is performed by achieving a four (or six) bit right shift and dropping the right most four (or six) bits.

44. 发明专利

CA1127309A OPTIMIZED DIGITAL DELTA MODULATION COMPANDER HAVING TRUNCATION EFFECT ERROR RECOVERY 未知
公开(公告)号：CA1127309A
公开(公告)日：1982-07-06
申请号：CA362763
申请日：1980-10-20
申请人： IBM
发明人： CROUSE WILLIAM G
IPC分类号： H03M3/02 , H03M7/34 , H04B14/06 , H03K13/22
摘要： AN OPTIMIZED DIGITAL DELTA MODULATION COMPANDER HAVING TRUNCATION EFFECT ERROR RECOVERY A digital delta modulation compander circuit makes advantageous use of the mathematical truncation created during the computation of step sizes to create a nonlinear step size variation which differs from the optimum desired step size but causes convergence recovery during error conditions. It has been discovered that the truncation involved in the inaccurate approximation of mathematical calculation of the step sizes produces an advantageous result which leads to an optimized digital delta modulation compander that will recover from transmission errors over a wider range and with greater efficiency than other methods. RA9-79-004

45. 发明专利

AU6321380A DELTA MODULATION COMPANDER 未知
公开(公告)号：AU6321380A
公开(公告)日：1981-06-25
申请号：AU6321380
申请日：1980-10-13
申请人： IBM
发明人： CROUSE W G
IPC分类号： H03M3/02 , H03M7/34 , H04B14/06 , H03K13/22 , H04B12/04
摘要： Delay circuits (21) and (22) and logic gates (23, 24, 25) provide an output which is representative of three successive like bits appearing on the compander input line. Multiplier (26) multiplies the current delta step value DELTA by /16 and multiplier (27) multiplies the same by - /64. When the output of logic gate (25) is a 1, (three like bits), AND gate (28) let the output of multiplier (26) apply to three input adder (31). The output of this adder then delivers a delta step signal When the output of logic gate (25) is a zero, the new delta step is since AND gate (28) does not deliver any output. Multipliers (26) and (27) are shift registers, and the division by 16 or 64 is performed by achieving a four (or six) bit right shift and dropping the right most four (or six) bits.

46. 发明专利

SU663100A1 DECODER 未知
公开(公告)号：SU663100A1
公开(公告)日：1979-05-15
申请号：SU2477142
申请日：1977-04-18
申请人： LE ELEKTROTEKH INST
发明人： YURGENSON ROBERT , KARATUN SERGEJ M , RYABININ VLADIMIR G
IPC分类号： H03M7/34 , H03K13/00

47. 发明专利

RU2009110512A СПОСОБ СЖАТИЯ ИЗОБРАЖЕНИЙ И ВИДЕОПОСЛЕДОВАТЕЛЬНОСТЕЙ 未知
公开(公告)号：RU2009110512A
公开(公告)日：2010-09-27
申请号：RU2009110512
申请日：2009-03-24
IPC分类号： H03M7/34 , H04N7/26 , H04N11/04
摘要： 1. Способкомпактногобитовогопредставлениявысококачественнойцветнойвидеопоследовательности, заключающийсяв блочномкодированиикаждогоцветноговидеокадравидеопоследовательности, вкоторомкаждыйцветнойпиксельпредставляюттремяцветовымикомпонентами, каждуюизкоторыхизначальнокодируютдесятьюбитами, отличающийсятем, чтокодированиеосуществляютпутемразбиенияисходногоцветноговидеокадрананеперекрывающиесяпространственныеблоки, состоящиеизболеечемодногопикселяпогоризонталии двухпикселейповертикали, последующегоразделениябитовогопредставлениякаждойизцветовыхкомпонентпикселянастаршуючасть, состоящуюизболеечемодногостаршегобита, имладшуючасть, состоящуюиз, поменьшеймере, одногомладшегобита, всуммеобразующихисходныедесятьбитов, раздельногокодированиястаршейи младшейчастей, причемкодированиестаршейчастиосуществляютпутемпримененияболееодногоспособакодирования, каждыйизкоторыхучитываетмежпиксельныесвязитольков пределахобрабатываемогопространственногоблокаи применяетсядлясокращенияколичествабитов, необходимыхдляпредставленияобрабатываемыхданных, оценкипогрешностикодирования, выбораспособакодирования, дающегонаименьшуюпогрешность, пересылкиданныхо способекодированияпосредствомпередачипрефиксногокода, кодированиимладшейчасти, котороеосуществляетсяпутемусредненияболееодногозначения, входящегов младшуючасть, причемразмерыобластейусредненияв пределахмладшейчастизависятотвыбранногометодакодированиястаршейчасти, изасчетвыбораспособакодированиястаршейчасти, обесп

48. 发明专利

AU2003239943A1 BI-QUAD DIGITAL FILTER CONFIGURED WITH A BIT BINARY RATE MULTIPLIER 未知
公开(公告)号：AU2003239943A1
公开(公告)日：2004-11-23
申请号：AU2003239943
申请日：2003-06-02
申请人： ESS TECHNOLOGY INC
发明人： MALLINSON ANDREW MARTIN
IPC分类号： H03H17/02 , H03M7/32 , H03M7/36 , H03M7/00 , H03M7/34
摘要： The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

49. 发明专利

DE69918313D1 未知
公开(公告)号：DE69918313D1
公开(公告)日：2004-07-29
申请号：DE69918313
申请日：1999-08-13
申请人： QUALCOMM INC
发明人： RIDDLE C , LEVIN A
IPC分类号： H03M7/24 , G06F7/48 , H03M7/34 , H03M7/00 , H03M3/02
摘要： A method and apparatus for compressing fixed point signals without introducing a bias. Signals are compressed according to a dithered rounding approach wherein signal values are rounded up and rounded down with approximately equal probability, canceling the bias that would otherwise result from the rounding operation. Numerical properties of the input signal are exploited in order to determine whether the signal value should be rounded up or down. Signal compression may, therefore, be introduced at multiple points within a system without accumulating a signal bias and degrading downstream performance. Further, one bit signal compression may be achieved in a particularly efficient fashion with a minimal amount of hardware.

50. 发明专利

AU2003285884A8 Adaptive multi-bit delta and sigma-delta modulation 未知
公开(公告)号：AU2003285884A8
公开(公告)日：2004-05-04
申请号：AU2003285884
申请日：2003-10-15
申请人： UNIV CALIFORNIA
发明人： SAYED ALI H , ALDAJANI MANSOUR A
IPC分类号： H03M3/00 , H03M7/30 , H03M7/34 , H04B14/06

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