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41. 发明申请

WO2010018533A2 ANALOG TO DIGITAL CONVERSION CIRCUIT WITH AUTOMATIC BIAS POINT DETERMINATION AND MR GRADIENT SYSTEMS USING THE SAME 审中-公开
标题翻译：模拟到具有自动偏心点确定的数字转换电路和使用其的MR梯度系统
公开(公告)号：WO2010018533A2
公开(公告)日：2010-02-18
申请号：PCT/IB2009/053516
申请日：2009-08-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH , SCHEEL, Thomas , HATTRUP, Christian , LUERKENS, Peter
发明人： SCHEEL, Thomas , HATTRUP, Christian , LUERKENS, Peter
CPC分类号： H03M3/412
摘要： A hybrid analog/digital circuit comprises: an analog difference element (60) configured to output an analog difference signal (d) corresponding to a difference between an input analog signal (s meas ) and an analog feedback signal (s bias ); an analog-to-digital converter (ADC) (62) configured to generate a multi-bit digital representation (D) of the analog difference signal; digital control circuitry (64, 66, 68) including at least a digital integrator or digital summer (64), the digital control circuitry configured to generate a digital control signal (S BIAS ) based on the multi-bit digital representation of the analog difference signal; a digital-to-analog converter (DAC) (70) configured to generate the analog feedback signal (s bias ) having an analog value corresponding to a digital value of the digital control signal; and an output unit (72, 74) arranged to output a digital output signal (S MEAS ) equal to or derived from the digital control signal.
摘要翻译：混合模拟/数字电路包括：模拟差分元件（60），被配置为输出对应于输入模拟信号（s meas）和模拟反馈信号（s bias）之间的差的模拟差分信号（d）; 被配置为产生所述模拟差分信号的多位数字表示（D）的模拟 - 数字转换器（ADC）（62）; 包括至少数字积分器或数字加法器（64）的数字控制电路（64,66,68），所述数字控制电路被配置为基于所述模拟差异的多位数字表示来生成数字控制信号（S BIAS）信号; 配置成产生具有对应于数字控制信号的数字值的模拟值的模拟反馈信号（s偏置）的数模转换器（DAC）（70）以及布置成输出与数字控制信号相等或从数字控制信号导出的数字输出信号（S MEAS）的输出单元（72,74）。

42. 发明申请

WO2008033686A2 ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A REDUCED NUMBER OF QUANTIZER OUTPUT LEVELS 审中-公开
标题翻译：模数转换器（ADC）具有减少数量的量测器输出电平
公开(公告)号：WO2008033686A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/077363
申请日：2007-08-31
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L.
IPC分类号： H03M3/04
CPC分类号： H03M3/412 , H03M3/424 , H03M3/452 , H03M3/454
摘要： An analog-to-digital converter provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter has a reduced number of quantizer output levels and includes a loop filter, a quantizer for quantizing the output of the loop filter and a digital integrator for integrating the output of the quantizer. A difference circuit is included in the converter that produces a signal proportional to the difference between the present value and a previous value of the digital integrator output and provides feedback to the loop filter. The number of levels of the quantizer output is thereby reduced with respect to the modulator output, since the quantizer is operating on a feedback signal that represents changes in the output of the converter modulator rather than the modulator output itself.
摘要翻译：模数转换器提供降低的复杂性和功耗以及改进的线性度。模数转换器具有减少的量化器输出电平数量，并且包括环路滤波器，用于量化环路滤波器的输出的量化器和用于积分量化器的输出的数字积分器。差分电路包括在转换器中，产生与当前值和数字积分器输出的先前值之间的差成比例的信号，并向环路滤波器提供反馈。量化器输出的电平数量因此相对于调制器输出而减少，因为量化器在表示转换器调制器的输出的变化而不是调制器输出本身的反馈信号上操作。

43. 发明专利

JP3857412B2 High-speed delta-sigma a / d converter 失效
公开(公告)号：JP3857412B2
公开(公告)日：2006-12-13
申请号：JP8668798
申请日：1998-03-31
申请人：テキサスインスツルメンツインコーポレイテツド
发明人：ナガラジクリシュナスワミイ , アール．ビスワナサンサヤムクランガラ , エル．マクドナルドチャールズ
IPC分类号： H03M3/02 , H03M1/12 , H03M7/32
CPC分类号： H03M3/412 , H03M3/456

44. 发明专利

JP2005510110A Sigma-delta modulation 审中-公开
公开(公告)号：JP2005510110A
公开(公告)日：2005-04-14
申请号：JP2003544912
申请日：2002-10-28
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人：アーセーエムニュエイテン，ペートルス , レーフマン，デルク
IPC分类号： H03M3/02 , H03M1/00 , H03M3/00
CPC分类号： H03M3/344 , H03M3/358 , H03M3/412
摘要：本発明により得られるシグマデルタ変調装置は、入力信号を第１のＳＤＭに与え、第１のＳＤＭの出力を入力信号から減算し、フィルタ処理された信号を得るために、減算出力をフィルタ処理し、入力信号を遅延させ、フィルタ処理された信号を遅延した入力信号に加算し、加算器の出力を第２のＳＤＭに与え、第２のＳＤＭの出力を供給する。減算及びフィルタリングの組合せにおける第１のＳＤＭは、入力信号にそれを加えることで、補正信号を出力し、第２のＳＤＭにて歪を減らし、第２のＳＤＭは装置の実際上のシグマデルタ変調を行なう。

45. 发明公开

KR1020040060979A 시그마-델타 변조 无效
标题翻译： Sigma-delta调制
公开(公告)号：KR1020040060979A
公开(公告)日：2004-07-06
申请号：KR1020047007370
申请日：2002-10-28
申请人： 코닌클리케 필립스 엔.브이.
发明人： 리프만더크 , 누이텐페트루스,에이.,씨.,엠.
IPC分类号： H03M3/02
CPC分类号： H03M3/344 , H03M3/358 , H03M3/412
摘要： 본 발명에 제 1 특징에 따른 시그마-델타 변조 방법은, 입력 신호를 제 1 SDM에 공급하고, 상기 입력 신호로부터 상기 제 1 SDM의 출력을 감산하고, 필터링된 신호를 얻기 위해 상기 감산기의 출력을 필터링하고, 상기 입력 신호를 지연하고, 상기 지연된 입력 신호에 상기 필터링된 신호를 가산하고, 제 2 SDM에 가산기의 출력을 공급하고, 상기 제 2 SDM의 출력을 공급한다. 상기 감산 및 상기 필터링과 결합한 상기 제 1 SDM은 수정 신호를 생성하고, 상기 수정 신호를 입력 신호에 가산함으로써 제 2 SDM에서의 왜곡을 감소하고, 제 2 SDM은 장치의 SDM을 실행한다.

46. 发明公开

KR1020030036677A 파이프라인 아날로그 디지털 컨버터 无效
标题翻译：空值
公开(公告)号：KR1020030036677A
公开(公告)日：2003-05-09
申请号：KR1020037001767
申请日：2002-06-05
申请人： 코닌클리케 필립스 엔.브이.
发明人： 로자엔겔
IPC分类号： H03M1/12
CPC分类号： H03M3/368 , H03M3/412
摘要： A multilayer substrate module to which an external ground node (20) supplies a reference ground potential (Vss) includes a plurality of ground lines (170-1, 170-2, 170-3), which correspond to a plurality of internal circuits (210, 220, 230), respectively. A common node (Ncmn) for joining the ground lines (170-1, 170-2, 170-3) is provided in an insulating layer (105C) in the multilayer substrate module. The common node (Ncmn) is coupled electrically to the ground node (20) through a ground pin terminal (204) shared among the internal circuits (210, 220, 230). The common node (Ncmn) is provided preferably in the lowermost insulating layer in the multilayer substrate module (120). The parasitic inductance appearing in a ground current path and shared among the internal circuits (210, 220, 230) can be decreased using fewer ground pin terminals. Therefore, the ground current path is prevented from being circuitous among the internal circuits (210, 220, 23O), resulting in stabilized operation.
摘要翻译：外部接地节点（20）提供参考接地电位（Vss）的多层衬底模块包括多个对应于多个内部电路的接地线（170-1,170-2,170-3） 210,220,230）。用于接合地线（170-1,170-2,170-3）的公共节点（Ncmn）设置在多层基板模块中的绝缘层（105C）中。公共节点（Ncmn）通过内部电路（210,220,230）中共享的接地引脚端子（204）电耦合到接地节点（20）。公共节点（Ncmn）优选地设置在多层基板模块（120）中的最下层的绝缘层中。可以使用更少的接地引脚端子来减小出现在接地电流路径中并在内部电路（210,220,230）之间共享的寄生电感。因此，防止接地电流路径在内部电路（210,220,230）之间迂回，导致稳定的操作。

47. 发明公开

US20240388308A1 ANALOG TO DIGITAL CONVERTER WITH VCO-BASED AND PIPELINED QUANTIZERS 审中-公开
公开(公告)号：US20240388308A1
公开(公告)日：2024-11-21
申请号：US18786120
申请日：2024-07-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M3/00 , H03K3/03
CPC分类号： H03M3/368 , H03K3/0315 , H03M3/412 , H03M3/464
摘要： An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

48. 发明申请

US20190245553A1 SIGMA DELTA MODULATOR, INTEGRATED CIRCUIT AND METHOD THEREFOR 审中-公开
公开(公告)号：US20190245553A1
公开(公告)日：2019-08-08
申请号：US15935045
申请日：2018-03-25
申请人： NXP B.V.
发明人： Muhammed BOLATKALE , Lucien Johannes BREEMS
IPC分类号： H03M3/00
CPC分类号： H03M3/424 , H03M1/001 , H03M1/12 , H03M3/30 , H03M3/37 , H03M3/412 , H03M3/42 , H03M3/464
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

49. 发明授权

US09276792B1 Phase-domain digitizer 有权
标题翻译：相域数字化仪
公开(公告)号：US09276792B1
公开(公告)日：2016-03-01
申请号：US14544841
申请日：2015-02-24
申请人： Stichting voor de Technische Wetenschappen
发明人： Kofi A. A. Makinwa , Rui Quan
IPC分类号： H04L27/00 , H04L27/233 , H04L7/00
CPC分类号： H04L27/2334 , G01F1/66 , H03L1/022 , H03L7/00 , H03L7/0814 , H03L7/085 , H03M3/412 , H03M3/464 , H03M3/496
摘要： A phase-domain delta-sigma (ΔΣ) modulator in a phase digitizer determines a demodulated phase error based on a phase-modulated frequency signal, in which a carrier frequency is modulated with a fundamental frequency and an associated phase, and a selected one of a set of reference signals, where the demodulated phase error represents a difference between the phase and a reference phase of the selected one of the set of reference signals. Moreover, a digital filter in the phase-domain ΔΣ modulator filters the demodulated phase error. Furthermore, a latch in the phase-domain ΔΣ modulator provides a bit stream by sampling one or more bits of the filtered demodulated phase error, where an average value of the bit stream represents the phase. Next, control logic in the phase-domain ΔΣ modulator selects the one of the set of reference signals.
摘要翻译：相位数字化仪中的相位Δ-Σ（＆Dgr＆amp; Sgr）调制器基于相位调制频率信号确定解调的相位误差，其中以基频和相关相位对载波频率进行调制，所选择的一组参考信号中的一个，其中解调的相位误差表示所述一组参考信号中的所选择的一个的相位和参考相位之间的差。此外，相域中的数字滤波器＆Dgr; 调制器滤波解调的相位误差。此外，相域中的锁存器＆Dgr; 调制器通过采样滤波的解调相位误差的一个或多个比特来提供比特流，其中比特流的平均值代表相位。接下来，相域中的控制逻辑＆Dgr＆调制器选择该组参考信号中的一个。

50. 发明授权

US08344921B2 Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method 有权
标题翻译：具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法
公开(公告)号：US08344921B2
公开(公告)日：2013-01-01
申请号：US13072797
申请日：2011-03-28
申请人： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
发明人： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/412 , H03M3/426 , H03M7/3042
摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。截断器接收数字信息并根据数字信息产生截断的信息。反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

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