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41. 发明公开

CN1462069A 布线结构的形成方法失效
公开(公告)号：CN1462069A
公开(公告)日：2003-12-17
申请号：CN03138207.X
申请日：2003-05-23
申请人：松下电器产业株式会社
发明人：原田刚史
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L21/76807 , H01L21/3212 , H01L21/76882 , H01L21/76886 , H01L2221/1036
摘要：本发明提供一种在半导体装置等的电子器件中的布线结构的形成方法。在FSG膜(105)等的绝缘膜上形成凹部(106)和布线槽(107)后在FSG膜(105)上使凹部(106)等埋入地沉积Cu膜。对于该Cu膜进行第1热处理并形成Cu膜(111)后，除去Cu膜(111)中凹部(106)等外侧部分。之后对于残存的Cu膜(111)以其表面露出的状态进行第2热处理。根据本发明，由于可以实现没有空洞或表面裂痕的布线结构，所以可以以高的成品率制造可靠性高的半导体装置的电子器件。

42. 发明公开

CN1428855A 半导体器件失效转让
公开(公告)号：CN1428855A
公开(公告)日：2003-07-09
申请号：CN02157548.7
申请日：2002-12-20
申请人：富士通株式会社
发明人：渡边健一 , 清水纪嘉 , 铃木贵志
IPC分类号： H01L23/522 , H01L21/768 , H01L21/3205
CPC分类号： H01L21/76811 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要：在此提供一种半导体器件，其中包括：第二绝缘膜，其形成在第一布线的表面与第二绝缘膜的表面相连续的一个基本上平整表面上，以覆盖第一布线；在第二绝缘膜中形成第一布线沟槽；在第二绝缘膜中形成的连接孔，以从该布线沟槽延伸到该第一布线；在第二绝缘膜中形成的伪连接孔，以从布线沟槽延伸到不形成第一布线的区域；以及第二布线，其被埋在该连接孔和布线沟槽中，以电连接到第一布线，并且还被埋在伪连接孔中，并且被形成为使得第二布线的表面与第一绝缘膜的表面构成一个基本上平整的表面。

43. 发明公开

CN1304172A 半导体器件的制造方法失效
公开(公告)号：CN1304172A
公开(公告)日：2001-07-18
申请号：CN00131478.5
申请日：2000-10-20
申请人：三菱电机株式会社
发明人：国清辰也
IPC分类号： H01L21/768 , H01L21/283 , H01L21/3205
CPC分类号： H01L21/76814 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L21/76819 , H01L21/76825 , H01L21/7684 , H01L21/76843 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要：降低相邻布线间产生的布线电容,获得半导体器件的制造方法。在形成TEOS膜1后,通过CVD法或PVD法,在TEOS膜1上形成FSG膜2。而且,为了稀有气体原子可进入膜中,继续FSG膜的CVD或PVD,形成稀有气体原子含有层3。接着,以稀有气体原子含有层3上形成的抗蚀剂4用作掩模,顺序地腐蚀稀有气体原子含有层3和FSG膜2。然后,在除去抗蚀剂4后,在整个表面上形成阻挡金属6和铜膜7。接着,通过CMP法,顺序地研磨除去铜膜和阻挡金属6,直至稀有气体原子含有层3的上表面露出。由此,作为未被研磨的残留铜膜7,形成填充沟5内的铜布线9。

44. 发明公开

CN1258097A 形成双镶嵌布线的方法无效
公开(公告)号：CN1258097A
公开(公告)日：2000-06-28
申请号：CN99126604.8
申请日：1999-12-21
申请人：日本电气株式会社
发明人：池田真义
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76808 , H01L21/76813 , H01L2221/1036
摘要：在形成双镶嵌布线方法中,在下导电层上形成层间绝缘膜,在层间绝缘膜中形成具有用于通孔图形的开口的抗蚀膜。用抗蚀膜作为掩模腐蚀层间绝缘膜,形成通孔,用腐蚀速率高于层间绝缘膜的材料填充通孔,形成埋置膜。然后,在埋置膜上形成具有用于布线沟槽图形的开口的抗蚀膜,用该抗蚀膜作为掩模,腐蚀埋置膜和层间绝缘膜,在层间绝缘膜上形成布线沟槽。该方法确保了不会留下层间绝缘膜的腐蚀残留物带来的杂质,可形成高质量的布线。

45. 发明申请

WO2009117670A3 SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS 审中-公开
标题翻译：用于互连的自对准障碍层
公开(公告)号：WO2009117670A3
公开(公告)日：2012-03-22
申请号：PCT/US2009037826
申请日：2009-03-20
申请人： HARVARD COLLEGE , GORDON ROY GERALD , KIM HOON
发明人： GORDON ROY GERALD , KIM HOON
IPC分类号： H01L21/768 , C23C16/16 , C23C16/18 , H01L21/285 , H01L23/532
CPC分类号： H01L21/76864 , C23C16/16 , C23C16/18 , H01L21/28556 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for integrated circuits incorporates manganese silicate (80) and manganese silicon nitride layers (60,90) that completely surrounds copper wires (20,120) in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper- manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese - containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.
摘要翻译：用于集成电路的互连结构包括在集成电路中完全围绕铜线（20,120）的硅酸锰（80）和锰氮化硅层（60,90）及其制造方法。硅酸锰形成阻止铜从电线中扩散的屏障，从而保护绝缘体免于过早击穿，并保护晶体管免受铜的退化。硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。铜锰硅酸盐和锰氮化硅界面处的强粘附性也可防止在使用设备期间铜的电迁移而导致故障。含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。

46. 发明申请

WO2009117670A2 SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS 审中-公开
标题翻译：用于互连的自对准障碍层
公开(公告)号：WO2009117670A2
公开(公告)日：2009-09-24
申请号：PCT/US2009/037826
申请日：2009-03-20
申请人： PRESIDENT AND FELLOWS OF HARVARD COLLEGE , GORDON, Roy, Gerald , KIM, Hoon
发明人： GORDON, Roy, Gerald , KIM, Hoon
IPC分类号： H01L21/768
CPC分类号： H01L21/76864 , C23C16/16 , C23C16/18 , H01L21/28556 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper- manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese- containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.
摘要翻译：用于集成电路的互连结构包括在集成电路中完全包围铜线的硅酸锰和锰氮化硅层，以及用于制造其的方法。硅酸锰形成阻止铜从电线扩散的屏障，从而保护绝缘体不被过早击穿，并保护晶体管免受铜的退化。硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。铜硅酸锰和锰硅氮化物界面的强粘附性也可防止铜在使用设备期间的电迁移而失效。含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。

47. 发明申请

WO02054483A3 A DUAL DAMASCENE INTEGRATION SCHEME USING A BILAYER INTERLEVEL DIELECTRIC 审中-公开
标题翻译：使用双层交互式电介质的双重DAMASCENE集成方案
公开(公告)号：WO02054483A3
公开(公告)日：2003-06-05
申请号：PCT/US0147376
申请日：2001-12-04
申请人： INFINEON TECHNOLOGIES CORP
发明人： KALTALIOGLU ERDEM
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76808 , H01L2221/1031 , H01L2221/1036
摘要： A semiconductor structure includes a semiconductor substrate and a dielectric layer disposed over the substrate, the dielectric layer having a first trench. A first metal layer is disposed in the first trench. A first layer of a material having a first dielectric constant is disposed over the dielectric layer, the first layer having a via in registration with the metal disposed in the first trench. A second layer of a material having a second dielectric constant is disposed over the first layer of material, the second layer having a second trench in registration with the via. The first dielectric constant is higher than the second dielectric constant. A second metal layer is disposed in the via and second trench, the second metal layer being in contact with the first metal layer.
摘要翻译：半导体结构包括半导体衬底和设置在衬底上的电介质层，电介质层具有第一沟槽。第一金属层设置在第一沟槽中。具有第一介电常数的材料的第一层设置在电介质层上，第一层具有通孔，该通孔与布置在第一沟槽中的金属对准。具有第二介电常数的材料的第二层设置在第一材料层之上，第二层具有与通孔对准的第二沟槽。第一介电常数高于第二介电常数。第二金属层设置在通孔和第二沟槽中，第二金属层与第一金属层接触。

48. 发明申请

WO01080309A2 A METHOD TO ENHANCE THE ADHESION OF SILICON NITRIDE TO LOW-K FLUORINATED AMORPHOUS CARBON USING A SILICON CARBIDE ADHESION PROMOTER LAYER 审中-公开
标题翻译：使用碳化硅粘合促进剂层增强氮化硅与低K氟化不定形碳的粘合的方法
公开(公告)号：WO01080309A2
公开(公告)日：2001-10-25
申请号：PCT/JP2001/002871
申请日：2001-04-02
IPC分类号： C23C16/26 , C23C16/32 , C23C16/34 , C23C16/42 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76832 , C23C16/325 , C23C16/345 , H01L21/0212 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/3127 , H01L21/314 , H01L21/3146 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L2221/1036
摘要： A plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits. The method comprises the steps of depositing a fluorinated amorphous carbon (a-F:C) layer (128) on a substrate (120). An adhesion promoter layer of relatively hydrogen-free hydrogeneated silicon carbide (126, 130) is then deposited on the a-F:C layer using silane (SiH4) and methane (CH4) as the deposition gases. The deposited silicon carbide layer (126, 130) has relatively few hyrogen bonds thereby yielding a compact structure which promotes adhesion to a silicon nitride layer (124, 132) and to the a-F:C layer (128), and which reduces diffusion of fluorine through the silicon carbide layer. A silicon nitride layer (132) having relatively few hydrogen bonds is then deposited on the adhesion promoter layer. This stacked layer structure has thermal stability and resists peeling and cracking up to 450 DEG C, and the a-F:C dielectric layer has a dielectric constant (k) as low, or lower, than 2.5.
摘要翻译：提供等离子体增强化学气相沉积（PECVD）工艺，用于在衬底上沉积用于集成电路的互连结构中的一个或多个介电材料层。该方法包括在衬底（120）上沉积氟化无定形碳（a-F：C）层（128）的步骤。然后使用硅烷（SiH4）和甲烷（CH4）作为沉积气体，在a-F：C层上沉积相对无氢的氢化碳化硅的粘附促进剂层（126,130）。沉积的碳化硅层（126,130）具有相对较少的氢键，由此产生促进与氮化硅层（124,132）和aF:C层（128）的粘附的紧凑结构，并且这降低了氟的扩散通过碳化硅层。然后将具有相对较少氢键的氮化硅层（132）沉积在粘附促进剂层上。该堆叠层结构具有热稳定性，抗剥落高达450℃，a-F：C介电层的介电常数（k）低于或低于2.5。

49. 发明授权

EP3076430B1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3076430B1
公开(公告)日：2017-08-30
申请号：EP16168570.6
申请日：2003-02-14
申请人： Fujitsu Semiconductor Limited
发明人： Watanabe, Kenichi , Kawano, Michiari , Namba, Hiroshi , Sukegawa, Kazuo , Hasegawa, Takumi , Sawada, Toyoji
IPC分类号： H01L23/58 , G03F1/26 , H01L21/768 , G03F1/32
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00

50. 发明授权

EP2264758B1 Interconnection structure in semiconductor device 有权
标题翻译：在半导体元件的连接结构
公开(公告)号：EP2264758B1
公开(公告)日：2017-03-01
申请号：EP10177318.2
申请日：2002-12-05
申请人： Fujitsu Semiconductor Limited
发明人： Watanabe, Kenichi , Shimizu, Noriyoshi , Suzuki, Takashi
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L21/76811 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L2221/1036 , H01L2924/0002 , H01L2924/00

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