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41. 发明申请

WO2018092981A2 고속의 NAF 변환 장치 및 고속의 NAF 변환 방법 审中-公开
公开(公告)号：WO2018092981A2
公开(公告)日：2018-05-24
申请号：PCT/KR2017/001113
申请日：2017-02-02
申请人： 부산대학교 산학협력단
发明人： 황두희 , 최윤호
IPC分类号： H03M7/04 , G06F7/533 , G06F21/46
CPC分类号： G06F7/5332 , G06F21/46 , H03M7/04
摘要： 본 발명은 고속의 NAF 변환 장치 및 고속의 NAF 변환 방법에 관한 것이다. 본 발명에 따른 고속의 NAF 변환 장치는, 윈도우의 값을 설정하는 설정부 및 공개키의 LSB(Least Significant Bit)를 기준으로, 상기 설정된 값을, 길이로 갖는 윈도우를, 상기 공개키의 적어도 일부에 제1 세팅하고, 상기 공개키 내 암호화 대상이 되는 타깃 비트가, 상기 윈도우의 밖에 있는 경우, 상기 타깃 비트가 포함되도록 상기 윈도우를, ω-비트 오른쪽 이동(ω-bit right shift)(상기 ω은 자연수)시켜, 상기 윈도우를 제2 세팅하는 처리부를 포함할 수 있다.

42. 发明申请

WO02019099A1 METHOD AND APPARATUS FOR INSTRUCTION SET ARCHITECTURE TO PERFORM PRIMARY AND SHADOW DIGITAL SIGNAL PROCESSING SUB-INSTRUCTIONS SIMULTANEOUSLY 审中-公开
标题翻译：用于执行主要和阴影数字信号处理指令的指导设置架构的方法和装置同时
公开(公告)号：WO02019099A1
公开(公告)日：2002-03-07
申请号：PCT/US2001/025905
申请日：2001-08-16
IPC分类号： G06F7/52 , G06F7/53 , G06F7/533 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F17/10 , G06F9/40 , G06F9/44 , G06F9/52
CPC分类号： G06F9/3877 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30192 , G06F9/381 , G06F9/382 , G06F9/383 , G06F9/3842 , G06F9/3853 , G06F9/3885 , G06F17/10
摘要： A single DSP instruction includes a pair of sub-instructions: primary DSP sub-instruction and a shadow DSP sub-instruction. The two sub-instructions are dyadic DSP instructions performing two operations in one cycle. The DSP operations include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX), and a no operation (NOP). Each signal processing unit includes a primary stage to execute a primary sub-instruction based on current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based on delayed data stored within registers in signal processing units. Control logic is used to control shadow selectors to select delayed data. The system executed DSP instrucitions by simultaneously executing primary DSP sub-instructions based on current data and shadow DSP sub-instructions based on delayed data with single DSP instruction thereby performing four operations per single instruction.
摘要翻译：单个DSP指令包括一对子指令：主DSP子指令和阴影DSP子指令。两个子指令是在一个周期内执行两个操作的二进制DSP指令。 DSP操作包括乘法指令（MULT），加法指令（ADD），最小化/最大化指令（MIN / MAX）和无操作（NOP）。每个信号处理单元包括基于当前数据执行主要子指令的主阶段和阴影阶段，以基于信号处理单元中存储在寄存器内的延迟数据来同时执行影子DSP子指令。控制逻辑用于控制阴影选择器以选择延迟数据。该系统通过基于基于具有单个DSP指令的延迟数据的当前数据和阴影DSP子指令同时执行主DSP子指令，从而对每个指令执行四个操作来执行DSP指令。

43. 发明申请

WO02001727A1 METHOD FOR CONVERTING THE BINARY REPRESENTATION OF A NUMBER IN A SIGNED BINARY REPRESENTATION 审中-公开
标题翻译：用于转换二进制表示中的数字的二进制表示的方法
公开(公告)号：WO02001727A1
公开(公告)日：2002-01-03
申请号：PCT/FR2001/001944
申请日：2001-06-20
IPC分类号： G06F7/533 , H03M7/12
CPC分类号： H03M7/12 , G06F7/5332
摘要： The invention concerns a method for converting in a signed binary representation (r'm, , r'0) of a number r based on a left-to-right processing of bits of the binary representation (r'm, , r'0) and enabling to obtain a representation equivalent to the so-called Reitwiesner representation. The use of such a conversion method with left-to-right arithmetic processing enables to improve their hardware implementation.
摘要翻译：本发明涉及一种用于基于二进制表示（r'm，...，r'0）的位的从左到右处理来转换数字r的有符号二进制表示（r'm，r'0）的方法），并且能够获得与所谓的Reitwiesner表示相当的表示。使用这种从左到右算术处理的转换方法能够改进其硬件实现。

44. 发明申请

WO01035238A1 METHOD AND APPARATUS FOR SATURATED MULTIPLICATION AND ACCUMULATION IN AN APPLICATION SPECIFIC SIGNAL PROCESSOR 审中-公开
标题翻译：应用特定信号处理器中饱和多项式和累积的方法与装置
公开(公告)号：WO01035238A1
公开(公告)日：2001-05-17
申请号：PCT/US2000/041353
申请日：2000-10-19
IPC分类号： G06F7/52 , G06F7/53 , G06F7/533 , G06F7/544 , G06F9/302 , G06F9/38 , G06F17/10 , G06F15/00 , G06F15/16
CPC分类号： G06F17/10 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operation may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface (206), a buffer memory (210), a core processor (200A-D) for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where network is used to transceive packetized data and voice.
摘要翻译：应用专用信号处理器（ASSP）执行向量化和非向量化操作。可以使用饱和乘法和累加操作来执行非向量化操作。 ASSP包括用于执行数字信号处理的串行接口（206），缓冲存储器（210），核心处理器（200A-D），其包括精简指令集计算机（RISC）处理器和四个信号处理单元。四个信号处理单元并行地执行数字信号处理算法，包括执行饱和乘法和累加操作。 ASSP用于电信接口设备，如网关。 ASSP非常适合在网络用于收发分组数据和语音的电信系统中处理语音和数据压缩/解压缩。

45. 发明公开

EP2608015A1 System and method for implementing a multiplication 有权转让
标题翻译：系统和Verfahren zurAusführungeiner Multiplikation
公开(公告)号：EP2608015A1
公开(公告)日：2013-06-26
申请号：EP11194899.8
申请日：2011-12-21
申请人： IMEC , Katholieke Universiteit Leuven K.U. Leuven R&D , Samsung Electronics Co., Ltd.
发明人： Fasthuber, Robert , Raghavan, Praveen , Catthoor, Francky
IPC分类号： G06F9/30 , G06F7/533
CPC分类号： G06F7/523 , G06F7/5332 , G06F9/3001 , G06F9/30025
摘要： The present invention relates to a system for performing a multiplication, said system arranged for receiving a first data value (10) and comprising
- means (20) for calculating at run time a set of instructions for performing a multiplication using said first data value,
- storage means (50) for storing the set of instructions calculated at run time,
- multiplication means (40) arranged for receiving a second data value (30) and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data value using said at least one instruction.
摘要翻译：本发明涉及一种用于执行乘法的系统，所述系统被安排用于接收第一数据值（10）并且包括 - 用于在运行时间计算用于使用所述第一数据值执行乘法的一组指令的装置（20） - 存储装置（50），用于存储在运行时间计算的指令集; - 乘法装置（40），被布置用于从所存储的指令集接收第二数据值（30）和至少一个指令，所述第一和第二数据值使用所述至少一个指令。

46. 发明授权

EP1323030B1 METHOD AND APPARATUS FOR INSTRUCTION SET ARCHITECTURE TO PERFORM PRIMARY AND SHADOW DIGITAL SIGNAL PROCESSING SUB-INSTRUCTIONS SIMULTANEOUSLY 有权
标题翻译：方法和设备的指令集架构为PRIMARY和阴影DIGITALSIGNALVERARBEITUNGSSUBBEFEHLEN同步实施
公开(公告)号：EP1323030B1
公开(公告)日：2010-03-17
申请号：EP01964189.3
申请日：2001-08-16
申请人： Intel Corporation
发明人： GANAPATHY, Kumar , KANAPATHIPILLAI, Ruban
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3877 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30192 , G06F9/381 , G06F9/382 , G06F9/383 , G06F9/3842 , G06F9/3853 , G06F9/3885 , G06F17/10
摘要： Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.

47. 发明授权

EP1866741B1 CANONICAL SIGNED DIGIT MULTIPLIER 有权
标题翻译：规范地DRAWN数字乘法器
公开(公告)号：EP1866741B1
公开(公告)日：2009-07-15
申请号：EP06727715.2
申请日：2006-03-23
申请人： NXP B.V.
发明人： PU, Tianyan , BI, Lei
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

48. 发明公开

EP1543408A1 VORRICHTUNG UND VERFAHREN ZUM BERECHNEN EINER MULTIPLIKATION MIT EINER VERSCHIEBUNG DES MULTIPLIKANDEN 有权
标题翻译：装置和方法用于计算乘以被乘数的转变
公开(公告)号：EP1543408A1
公开(公告)日：2005-06-22
申请号：EP03782247.5
申请日：2003-11-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-PierreINTEL Corporation , SEDLAK, Holger
IPC分类号： G06F7/72
CPC分类号： G06F7/722 , G06F7/5332
摘要： A device for calculating a modular multiplication comprises a unit for analyzing (100) positions of the multiplier by using a look-ahead algorithm in order to obtain a multiplication shifting value (sm). In addition, a unit for determining (104) an intermediate result shifting value is provided that determines a positive intermediate result shifting value. A unit (106) then calculates a multiplicand shifting value (sc) as a difference between the intermediate result shifting value (sz) and the multiplication shifting value (sm). The intermediate result from the previous iteration step and from the multiplicand are then shifted (108) by the corresponding shifting quantities (sc and sz) in order to then carry out a three-operand addition (112) with the shifted values optionally while taking look-ahead parameters (vn and vc) into consideration. The shifting of the intermediate result and of the multiplicand with regard to a fixed module enables the more efficient use of shifters since the multiplication shifting value (sm), which has a tendency to be large, does not dictate the shifter dimensioning.

49. 发明公开

EP1228442A4 METHOD AND APPARATUS FOR SATURATED MULTIPLICATION AND ACCUMULATION IN AN APPLICATION SPECIFIC SIGNAL PROCESSOR 审中-公开
标题翻译：方法和设备饱和乘法器和积累应用程序中的特定信号处理器
公开(公告)号：EP1228442A4
公开(公告)日：2004-06-02
申请号：EP00989667
申请日：2000-10-19
申请人： INTEL CORP
发明人： GANAPATHY KUMAR , KANAPATHIPIILLAI RUBAN
IPC分类号： G06F7/52 , G06F7/53 , G06F7/533 , G06F7/544 , G06F9/302 , G06F9/38 , G06F17/10
CPC分类号： G06F17/10 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operation may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface (206), a buffer memory (210), a core processor (200A-D) for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where network is used to transceive packetized data and voice.

50. 发明公开

EP1323026A1 METHOD AND APPARATUS FOR FLEXIBLE DATA TYPES 有权
标题翻译：方法和装置灵活的数据类型
公开(公告)号：EP1323026A1
公开(公告)日：2003-07-02
申请号：EP01962212.5
申请日：2001-08-16
申请人： INTEL CORPORATION
发明人： GANAPATHY, Kumar , KANAPATHIPILLAI, Ruban
IPC分类号： G06F7/38 , G06F7/49 , G06F7/60 , G06F9/302 , G06F9/315
CPC分类号： G06F9/383 , G06F5/00 , G06F7/4806 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F7/57 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/381 , G06F9/3816 , G06F9/382 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F17/10
摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the present invention includes flexible data typing, permutation, and type matching operations (1101, 1102, 1104 and 1106). The flexible data typing, permutation and type matching of operands provides programming flexibility to support different filtering and DSP algorithms having different types of filter coefficients or data samples. A data typer and aligner within each signal processing unit within the ASSP supports flexible data typing, permutation, and type matching of operands of the instruction set architecture.

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