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41. 发明授权

US06828623B1 Floating gate memory device with homogeneous oxynitride tunneling dielectric 有权
标题翻译：具有均匀氧氮化物隧道电介质的浮栅存储器件
公开(公告)号：US06828623B1
公开(公告)日：2004-12-07
申请号：US10232487
申请日：2002-08-30
申请人： Xin Guo , Nian Yang , Zhigang Wang
发明人： Xin Guo , Nian Yang , Zhigang Wang
IPC分类号： H01L29788
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/7885
摘要： A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.
摘要翻译：具有均匀氧氮化物隧道电介质的存储器件。具体地，本发明描述了一种闪存单元，其包括包括均匀氮氧化物的隧道氧化物介电层。隧道氧化物电介质层将浮置栅极与形成在衬底中的源极区域和漏极区域之间的沟道区域分离。闪存单元还包括将控制栅极与浮动栅极分离的介质层。在一种情况下，均匀的氮氧化合物是无缺陷的氮化硅。氧氮化物的均匀性是由于氮化物在隧道氧化物介电层内的均匀分布。此外，为了提高性能，使用均匀的氮氧化物可以增加介电常数并降低隧道氧化物介电层的势垒高度。此外，均匀的氮氧化物支持闪存单元中的源极侧通道热孔擦除。

42. 发明授权

US06822259B1 Method of detecting and distinguishing stack gate edge defects at the source or drain junction 有权
标题翻译：在源极或漏极结处检测和区分堆叠栅极边缘缺陷的方法
公开(公告)号：US06822259B1
公开(公告)日：2004-11-23
申请号：US10126193
申请日：2002-04-19
申请人： Zhigang Wang , Nian Yang , Xin Guo
发明人： Zhigang Wang , Nian Yang , Xin Guo
IPC分类号： H01L2358
CPC分类号： H01L21/28273 , G11C16/04 , G11C29/006 , G11C2029/0403 , G11C2029/5002
摘要： A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.
摘要翻译：一种用于测试包括堆叠浮栅结构的半导体的方法和装置。浮动门被编程（710）。电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。在应力之后，测量漏极电流与栅极电压的关系（730）。编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

43. 发明授权

US06797650B1 Flash memory devices with oxynitride dielectric as the charge storage media 有权
标题翻译：具有氧氮化物介质的闪存器件作为电荷存储介质
公开(公告)号：US06797650B1
公开(公告)日：2004-09-28
申请号：US10342032
申请日：2003-01-14
申请人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
发明人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518
摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.
摘要翻译：本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

44. 发明授权

US06646462B1 Extraction of drain junction overlap with the gate and the channel length for ultra-small CMOS devices with ultra-thin gate oxides 失效
标题翻译：漏极结的提取与具有超薄栅极氧化物的超小型CMOS器件的栅极和沟道长度重叠
公开(公告)号：US06646462B1
公开(公告)日：2003-11-11
申请号：US10178144
申请日：2002-06-24
申请人： Nian Yang , Zhigang Wang , Xin Guo
发明人： Nian Yang , Zhigang Wang , Xin Guo
IPC分类号： H01L2998
CPC分类号： H01L22/34 , H01L29/7836 , H01L2924/0002 , H01L2924/00
摘要： The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated. The source/drain junction overlap length is then used to calculate the channel length of the small device.
摘要翻译：本发明一般涉及一种确定诸如MOS晶体管的小器件的源/漏结重叠和沟道长度的方法。提供具有已知通道长度的大参考装置，并且其上形成有装置的源极，漏极和基板接地。将预定的栅极电压施加到大型器件的栅极，并测量参考器件的栅极到沟道电流。形成小型器件的源极，漏极和衬底接地，并且将预定电压施加到小器件的栅极，并且测量小器件的栅极到沟道电流。衬底和小器件的源极或漏极中的一个浮置，并且将预定的漏极电压施加到不浮动的源极或漏极。测量用于小器件的漏极电流的栅极，并计算源极/漏极结重叠长度。然后使用源极/漏极结重叠长度来计算小器件的沟道长度。

45. 发明授权

US06570787B1 Programming with floating source for low power, low leakage and high density flash memory devices 有权
标题翻译：使用浮动源编程，实现低功耗，低泄漏和高密度闪存设备
公开(公告)号：US06570787B1
公开(公告)日：2003-05-27
申请号：US10126330
申请日：2002-04-19
申请人： Zhigang Wang , Nian Yang , Xin Guo
发明人： Zhigang Wang , Nian Yang , Xin Guo
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.
摘要翻译：本发明涉及一种闪存阵列架构，其包括以NOR型阵列配置布置的多个闪存单元。多个闪存单元中的每一个具有耦合在一起以形成公共源的源极端子。阵列结构还包括耦合在阵列的公共源和预定电位之间的公共源选择部件。公共源选择组件可操作以将公共源耦合到处于第一状态的预定电位，并且在第二状态下将公共源与预定电位电隔离或浮动，从而减少与激活位相关联的未选择单元的泄漏在程序运行模式下运行。

46. 发明授权

US06472236B1 Determination of effective oxide thickness of a plurality of dielectric materials in a MOS stack 失效
标题翻译：确定MOS堆叠中多个介电材料的有效氧化物厚度
公开(公告)号：US06472236B1
公开(公告)日：2002-10-29
申请号：US09904740
申请日：2001-07-13
申请人： Zhigang Wang , Nian Yang , Tien-Chun Yang
发明人： Zhigang Wang , Nian Yang , Tien-Chun Yang
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks. A respective total effective oxide thickness, EOTMOS, is measured for each of the first plurality of test MOS stacks. A first graph having total effective oxide thickness as a first axis and having deposition time for forming the first dielectric structure as a second axis is generated by plotting the respective total effective oxide thickness, EOTMOS, versus the respective deposition time for forming the respective first dielectric structure for each of the first plurality of test MOS stacks. The respective second effective oxide thickness of the respective second dielectric structure that is substantially same for each of the first plurality of test MOS stacks is determined from an intercept of the first axis of total effective oxide thickness when deposition time for forming the first dielectric structure of the second axis is substantially zero in the first graph.
摘要翻译：用于确定形成MOS（金属氧化物半导体）堆叠的第一和第二电介质结构中的每一个的相应有效氧化物厚度的系统和方法。形成第一多个测试MOS（金属氧化物半导体）堆叠，并且每个测试MOS堆叠包括由第一电介质材料和由第二电介质材料组成的相应的第二电介质结构的相应的第一电介质结构。形成对应于第一多个测试MOS堆叠中的每一个的相应的第一介电结构的各自的沉积时间被改变，使得相应的第一介电结构的相应的第一有效氧化物厚度对于第一多个测试MOS堆叠而言是变化的。相应的第二介电结构的相应的第二有效氧化物厚度被保持为对于第一多个测试MOS堆叠中的每一个基本相同。对于第一多个测试MOS堆叠中的每一个测量相应的总有效氧化物厚度EOTMOS。通过绘制相应的总有效氧化物厚度EOTMOS，相对于形成相应的第一电介质的相应沉积时间，产生具有总有效氧化物厚度作为第一轴并具有用于形成第一电介质结构作为第二轴的沉积时间的第一图所述第一多个测试MOS堆叠中的每一个的结构。对于第一多个测试MOS堆叠中的每一个基本上相同的相应的第二介电结构的相应的第二有效氧化物厚度是从形成第一介电结构的沉积时间的总有效氧化物厚度的第一轴的截距来确定的在第一图中第二轴基本为零。

47. 发明授权

US09585550B2 Rectal expander 有权
标题翻译：直肠扩张器
公开(公告)号：US09585550B2
公开(公告)日：2017-03-07
申请号：US10561649
申请日：2004-06-24
申请人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
发明人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
IPC分类号： A61M29/00 , A61B1/32 , A61B1/31
CPC分类号： A61B1/32 , A61B1/31 , A61M29/00
摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).
摘要翻译：公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12）），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

48. 发明授权

US08864645B2 Hearing implant 有权
标题翻译：听力植入
公开(公告)号：US08864645B2
公开(公告)日：2014-10-21
申请号：US11795137
申请日：2006-01-13
申请人： Eric William Abel , Zhigang Wang
发明人： Eric William Abel , Zhigang Wang
IPC分类号： H04R25/02
CPC分类号： H04R25/606 , A61F2002/183 , H04R17/02
摘要： The present invention concerns an actuator for an implantable hearing aid for implantation into the human middle ear. The actuator comprises a substantially elongate piezoelectric component (34, 36) having first and second operating end faces (41, 43), said end faces extending substantially at right angles to the longitudinal axis of the piezoelectric component. Also there is provided a frame component comprising at least one flextensional amplifier element (32), the flextensional amplifier element being integral with and connecting first and second frame end portions (42, 44), the first and second frame end portions also extending substantially at right angles to longitudinal axis of the piezoelectric component when fitted thereto, whereby the first and second end portions are in contact with the piezoelectric component end faces.
摘要翻译：本发明涉及用于植入人中耳的可植入助听器的致动器。致动器包括具有第一和第二操作端面（41,43）的基本上细长的压电元件（34,36），所述端面基本上与压电元件的纵向轴线成直角延伸。还提供了一种包括至少一个张力放大器元件（32）的框架部件，该屈曲放大器元件与第一和第二框架端部（42,44）成一体并且连接第一和第二框架端部（42,44），第一和第二框架端部也基本上延伸与压电部件的纵轴成直角，由此第一和第二端部与压电元件端面接触。

49. 发明授权

US08742175B2 Para—or meso-functionalized aromatic ketone compounds, preparation methods thereof, and photopolymerization initiators comprising the same 有权
标题翻译：对 - 或内消旋官能化芳族酮化合物，其制备方法和包含它们的光聚合引发剂
公开(公告)号：US08742175B2
公开(公告)日：2014-06-03
申请号：US13695600
申请日：2011-11-04
申请人： Yongbo Zhang , Yanchao Wang , Yapeng Wang , Huaihai Song , Zhigang Wang
发明人： Yongbo Zhang , Yanchao Wang , Yapeng Wang , Huaihai Song , Zhigang Wang
IPC分类号： C07C49/00 , C07C45/00 , C07C211/00 , C07C217/00 , C07C261/00
CPC分类号： C08F2/50 , C07C49/784 , C07C49/83 , C07C49/84 , C07C59/90 , C07C62/38 , C07C69/16 , C07C69/18 , C07C69/30 , C07C69/54 , C07C69/75 , C07C69/757 , C07C69/82 , C07C225/16 , C07C229/60 , C07C323/22 , C07C2601/14 , C07D207/404 , C07D209/48 , C07D251/30 , C07F7/1804 , C08F2/48
摘要： The present invention discloses novel aromatic ketone compounds with functional substitution groups at para- or meta positions which can be used as photo-initiators or effective components of photo-initiator mixtures for the photopolymerizations of ethylenically unsaturated systems. The preparation of these compounds is also disclosed.
摘要翻译：本发明公开了具有在对位或间位具有官能取代基的新型芳族酮化合物，其可用作光引发剂或光引发剂混合物的有效成分，用于烯属不饱和体系的光聚合。还公开了这些化合物的制备。

50. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

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