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41. 发明授权

US08680941B2 Microwave harmonic processing circuit 有权
标题翻译：微波谐波处理电路
公开(公告)号：US08680941B2
公开(公告)日：2014-03-25
申请号：US13496259
申请日：2010-09-07
申请人： Kenta Kuroda , Kazuhiko Honjo
发明人： Kenta Kuroda , Kazuhiko Honjo
IPC分类号： H03H7/38
CPC分类号： H01P1/2039 , H01P1/268 , H03F1/0205 , H03F1/56 , H03F3/601 , H03F2200/387 , H03F2200/423
摘要： A microwave harmonic processing circuit includes (n−1) parallel open ended stubs differing in length, connected in parallel to an output terminal of a serial transmission line at a single point, and having predetermined electrical lengths corresponding to second to higher n-th (n is any integer) harmonics, respectively, the serial transmission line having an input terminal connected to an output terminal of a transistor and having a predetermined electrical length; a first strip conductor connecting the serial transmission line to two parallel open ended stubs of the (n−1) parallel open ended stubs at a single connecting point; a second strip conductor connecting the (n−3) parallel open ended stubs to each other at a single connecting point; a ground layer disposed between first strip conductor and second strip conductor; and a via electrically connecting a connecting portion of first strip conductor and a connecting portion of second strip conductor.
摘要翻译：微波谐波处理电路包括长度不同的（n-1）个并行开放短截线，并联连接到串行传输线的单个输出端的输出端，并且具有对应于第二至第n（ n是任何整数）谐波，串联传输线具有连接到晶体管的输出端并具有预定电长度的输入端; 将串联传输线连接到（n-1）个并联开放端短截线的两个平行的开端短管的第一带状导体，在单个连接点处; 在（n-3）个平行的开放端子的单个连接点处彼此连接的第二带状导体; 设置在第一带状导体和第二带状导体之间的接地层; 以及将第一带状导体的连接部和第二带状导体的连接部电连接的通路。

42. 发明授权

US08154348B2 Amplifier circuit 有权
标题翻译：放大器电路
公开(公告)号：US08154348B2
公开(公告)日：2012-04-10
申请号：US12872589
申请日：2010-08-31
申请人： Kazuhiko Honjo , Yoichiro Takayama , Ryo Ishikawa
发明人： Kazuhiko Honjo , Yoichiro Takayama , Ryo Ishikawa
IPC分类号： H03F3/191
CPC分类号： H03F3/60 , H03F1/56 , H03F3/66 , H03F2200/387 , H03F2200/391 , H03F2200/402
摘要： An amplifier circuit operating at a fundamental angular frequency •0, includes: a transistor which is represented by an equivalent circuit which includes: an equivalent output current source, a drain-source capacitor as a parallel parasitic capacitor to an output node of the equivalent output current source, and a drain inductor as serial parasitic inductor connected between the equivalent output current source and a drain output node; a harmonic frequency processing circuit which includes an input node connected with the drain output node and an output node; a resonant circuit section provided between the output node of the harmonic frequency processing circuit and a ground node and comprising (2n+1) resonators which have resonance frequencies different from each other; and a load resistance provided in a back stage of the harmonic frequency processing circuit. The resonance frequencies of the (2n+1) resonators are coincident with frequencies of (n+1) poles and n zeros formed between the drain output node and the ground node in the transistor when the output node of the harmonic frequency processing circuit is short-circuited to the ground node.
摘要翻译：以基角角频率工作的放大器电路，包括：由等效电路表示的晶体管，该等效电路包括：等效输出电流源，作为并联寄生电容器的漏源电容器到等效输出的输出节点电流源和漏极电感，作为连接在等效输出电流源和漏极输出节点之间的串联寄生电感; 谐波频率处理电路，其包括与所述漏极输出节点连接的输入节点和输出节点; 谐振电路部分，设置在谐波频率处理电路的输出节点和接地节点之间，并且包括具有彼此不同的共振频率的（2n + 1）个谐振器; 以及设置在谐波频率处理电路的后级中的负载电阻。当谐波频率处理电路的输出节点短路时，（2n + 1）谐振器的谐振频率与晶体管中的漏极输出节点和接地节点之间形成的（n + 1）极和n个零点的频率一致 - 通向地面节点。

43. 发明申请

US20100288540A1 THREE-DIMENSIONAL WIRING BOARD 失效
标题翻译：三维接线板
公开(公告)号：US20100288540A1
公开(公告)日：2010-11-18
申请号：US12808107
申请日：2009-01-16
申请人： Kazuhiko Honjo , Tadashi Nakamura
发明人： Kazuhiko Honjo , Tadashi Nakamura
IPC分类号： H05K1/03
CPC分类号： H05K3/462 , H05K1/183 , H05K3/4069 , H05K3/4697 , H05K2201/0133 , H05K2201/0209 , H05K2201/09154 , H05K2201/10378 , H05K2203/061 , H05K2203/063 , H05K2203/068
摘要： A three-dimensional circuit board includes a lower substrate, a connection layer provided on an upper surface of the lower substrate, and an upper substrate provided on an upper surface of the connection layer. The connection layer exposes a portion of the upper surface of the lower substrate. The connection layer includes an insulating layer having a through-hole, and a via-conductor made of conductive material filling the through-hole. A recess is provided directly above the portion of the upper surface of the lower substrate and is surrounded by a side surface of the upper substrate and a side surface of the connection layer. A portion of the upper surface of the connection layer connected to the side surface of the connection layer inclines in a direction toward the portion of the upper surface of the lower substrate. The portion of the upper surface of the connection layer is provided from the side surface of the connection layer to the via-conductor. A portion of an upper substrate of the upper substrate connected to the side surface of the upper substrate inclines in a direction toward the portion of the upper surface of the lower substrate. The circuit board allows a component to be mounted in the recess efficiently.
摘要翻译：三维电路板包括下基板，设置在下基板的上表面上的连接层和设置在连接层的上表面上的上基板。连接层露出下部基板的上表面的一部分。连接层包括具有通孔的绝缘层和由填充通孔的导电材料制成的通孔导体。在下基板的上表面的正上方设置凹部，被上基板的侧面和连接层的侧面包围。连接到连接层的侧表面的连接层的上表面的一部分在朝向下基板的上表面的部分的方向上倾斜。连接层的上表面的部分从连接层的侧表面提供到通孔导体。连接到上基板的侧表面的上基板的上基板的一部分在朝向下基板的上表面的部分的方向上倾斜。电路板允许组件有效地安装在凹槽中。

44. 发明申请

US20100155119A1 PASSIVE COMPONENT INCORPORATING INTERPOSER 有权
标题翻译：被动组件插入插座
公开(公告)号：US20100155119A1
公开(公告)日：2010-06-24
申请号：US12089124
申请日：2007-11-27
申请人： Tatsuo Sasaoka , Yasuhiro Sugaya , Eiji Kawamoto , Kazuhiko Honjo , Toshiyuki Asahi , Chie Sasaki , Hiroaki Suzuki
发明人： Tatsuo Sasaoka , Yasuhiro Sugaya , Eiji Kawamoto , Kazuhiko Honjo , Toshiyuki Asahi , Chie Sasaki , Hiroaki Suzuki
IPC分类号： H05K1/00
CPC分类号： H05K1/186 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/181 , H01L2924/19041 , H05K3/4652 , H05K2201/10636 , H05K2203/063 , Y02P70/611 , Y10T29/4913 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting of a semiconductor element (9).
摘要翻译：无源部件并入插入体包括：双面电路板（1），其两侧具有布线层（8）;无源部件（2），安装在双面电路板的一个表面上的布线层（8）上; （1），安装有无源部件（2）的双面电路板（1）的表面上层压由机织织物或无纺布或无机填料制成的第二绝缘层（3）和层压在所述双面电路板（1）的表面上的热固性树脂，第一绝缘层（4）由机织织物或无纺织物或无机填料制成，以及层压在未安装无源部件（2）的双面电路板（1）的另一表面上的热固性树脂，第一和第二布线形成在第一和第二绝缘层（3,4）上的层（5,6）和用于电连接设置在双面电路板（1）的两个表面上的布线层（8）的通孔（7）以及第一布线层（5）为fo的第一和第二布线层（5,6）以使得能够安装半导体元件（9）。

45. 发明申请

US20100147569A1 COMPONENT-EMBEDDED PRINTED WIRING BOARD 审中-公开
标题翻译：组件嵌入式印刷线路板
公开(公告)号：US20100147569A1
公开(公告)日：2010-06-17
申请号：US12709573
申请日：2010-02-22
申请人： Kazuhiko Honjo , Toshihiko Mori , Eiji Kawamoto , Junichi Kimura , Motoyoshi Kitagawa
发明人： Kazuhiko Honjo , Toshihiko Mori , Eiji Kawamoto , Junichi Kimura , Motoyoshi Kitagawa
IPC分类号： H05K1/00
CPC分类号： H05K1/186 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , H01L2924/3511 , H05K3/284 , H05K3/4652 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , H01L2224/0401
摘要： A component-embedded printed wiring board (PWB) is disclosed. This PWB includes (a) a fluid-resin embedding section formed at a location corresponding to electronic components such that the embedding section covers the electronic components, (b) a resin flow-speed accelerator placed in parallel with a top face of a circuit board and surrounding the embedding section, and (c) bonding resin placed at least between the accelerator and the circuit board. The fluid resin embedding section is filled up with the same resin as the bonding resin. This structure allows the accelerator to compress the resin with pressure applied to the PWB, so that the resin tends to flow along the circuit board. As a result, the fluid-resin embedding section is thoroughly filled up with the resin without leaving any air, and the reliable PWB is thus obtainable.
摘要翻译：公开了一种组件嵌入式印刷电路板（PWB）。该PWB包括（a）在与电子部件相对应的位置处形成的流体树脂嵌入部，使得嵌入部覆盖电子部件，（b）与电路基板的顶面平行放置的树脂流速加速器并且包围所述嵌入部分，以及（c）至少在所述加速器和所述电路板之间配置树脂。流体树脂嵌入部分填充与粘合树脂相同的树脂。这种结构允许加速器在施加到PWB上的压力下压缩树脂，使得树脂趋于沿着电路板流动。结果，流体树脂嵌入部分被树脂充分填充而不会留下任何空气，从而可获得可靠的PWB。

46. 发明申请

US20060261472A1 Multilayer module and method of manufacturing the same 失效
标题翻译：多层模块及其制造方法
公开(公告)号：US20060261472A1
公开(公告)日：2006-11-23
申请号：US11435716
申请日：2006-05-18
申请人： Junichi Kimura , Kazuhiko Honjo , Eiji Kawamoto , Shinji Harada , Motoyoshi Kitagawa
发明人： Junichi Kimura , Kazuhiko Honjo , Eiji Kawamoto , Shinji Harada , Motoyoshi Kitagawa
IPC分类号： H01L23/34
CPC分类号： H05K1/144 , H01L23/49827 , H01L23/5384 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/16225 , H01L2224/97 , H01L2225/06517 , H01L2225/06548 , H01L2225/06565 , H01L2225/06572 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/1627 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H01L2924/3511 , H05K1/0237 , H05K1/185 , H05K3/0052 , H05K3/3436 , H05K3/403 , H05K3/42 , H05K2201/09181 , H05K2201/10371 , H05K2201/10666 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A multilayer module which includes parts-containing module whose circuit board has been mounted at one surface with electronic component and the electronic component is covered with resin layer. Connection terminals have been provided either at resin layer or at the other surface of circuit board, also through hole has been provided for connection between the two surfaces of module. Also included is module, which has been provided with connection terminals at a place corresponding to connection terminal, and through hole for connection between the connection terminals and electronic component. Disposed between conductor layer and conductor layer is insulation layer, which insulation layer having conductive bond for connection between connection terminals, respectively. In the above-described configuration, places of through hole and electronic component in module are not restricted by a location of through hole.
摘要翻译：一种多层模块，其包括其电路板已经在一个表面上安装有电子部件并且电子部件被树脂层覆盖的部件容纳模块。已经在树脂层或电路板的另一表面设置了连接端子，并且还提供了用于在模块的两个表面之间连接的通孔。还包括在对应于连接端子的位置处设置有连接端子的模块和用于连接端子和电子部件之间的连接的通孔。在导体层和导体层之间设置绝缘层，绝缘层分别具有用于连接端子之间连接的导电接合层。在上述结构中，模块中的通孔和电子部件的位置不受通孔的位置的限制。

47. 发明申请

US20060260122A1 Component-embedded printed wiring board and method of manufacturing the same 失效
标题翻译：组件嵌入式印刷电路板及其制造方法
公开(公告)号：US20060260122A1
公开(公告)日：2006-11-23
申请号：US11434763
申请日：2006-05-17
申请人： Kazuhiko Honjo , Toshihiko Mori , Eiji Kawamoto , Junichi Kimura , Motoyoshi Kitagawa
发明人： Kazuhiko Honjo , Toshihiko Mori , Eiji Kawamoto , Junichi Kimura , Motoyoshi Kitagawa
IPC分类号： H05K1/00 , H05K3/00
CPC分类号： H05K1/186 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , H01L2924/3511 , H05K3/284 , H05K3/4652 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , H01L2224/0401
摘要： A component-embedded printed wiring board (PWB) is disclosed. This PWB includes (a) a fluid-resin embedding section formed at place corresponding to electronic components such that the embedding section covers the electronic components, (b) a resin flow-speed accelerator placed in parallel with a top face of a circuit board and surrounding the embedding section, and (c) bonding resin placed at least between the accelerator and the circuit board. The fluid resin embedding section is filled up with the same resin as the bonding resin. This structure allows the accelerator to compress the resin with a pressure applied to the PWB, so that the resin tends to flow along the circuit board. As a result, the fluid-resin embedding section is thoroughly filled up with the resin without leaving any airs, and the reliable PWB is thus obtainable.
摘要翻译：公开了一种组件嵌入式印刷电路板（PWB）。该PWB包括（a）在与电子部件对应的位置处形成的流体树脂嵌入部，使得嵌入部覆盖电子部件，（b）与电路基板的顶面平行设置的树脂流速加速器，围绕所述嵌入部分，以及（c）至少在所述加速器和所述电路板之间配置树脂。流体树脂嵌入部分填充与粘合树脂相同的树脂。这种结构允许加速器以施加到PWB的压力来压缩树脂，使得树脂趋于沿着电路板流动。结果，流体树脂嵌入部分被树脂充分填充而不留下任何空气，从而可获得可靠的PWB。

48. 发明授权

US5473281A Amplifier circuit having impedance matching circuit 失效
标题翻译：具有阻抗匹配电路的放大器电路
公开(公告)号：US5473281A
公开(公告)日：1995-12-05
申请号：US309393
申请日：1994-09-20
申请人： Kazuhiko Honjo
发明人： Kazuhiko Honjo
IPC分类号： H03F3/60
CPC分类号： H03F3/60
摘要： An amplifier circuit having an impedance matching circuit coupled between a transistor having an element impedance of Z.sub.Tr and a first transmission line having a characteristic impedance of Z.sub.0, the impedance matching circuit including a second transmission line having a characteristic impedance Z.sub.T0 .apprxeq.(Z.sub.Tr .times.Z.sub.0).sup.1/2 and a length of a quarter wavelength, and a high-harmonic processing circuit disposed at the connection of the second transmission line to the first transmission line. The high-harmonic component processing circuit has two parallel stubs each having a certain characteristic impedance and a released tip end, the two parallel stubs having length of one-eighth wavelength and one-twelfth wavelength, respectively.
摘要翻译：一种具有耦合在具有ZTr的元件阻抗的晶体管和具有Z0的特性阻抗的第一传输线的阻抗匹配电路的放大器电路，所述阻抗匹配电路包括具有特性阻抗ZT0 APPROX（ZTrxZ0）1 / 2和四分之一波长的长度，以及设置在第二传输线与第一传输线的连接处的高次谐波处理电路。高次谐波分量处理电路具有分别具有一定特性阻抗的两个并联短截线和释放的尖端，两个平行短截线长度分别为八分之一波长和十二分之一波长。

49. 发明授权

US4779127A Three-dimensional integrated circuit 失效
标题翻译：三维集成电路
公开(公告)号：US4779127A
公开(公告)日：1988-10-18
申请号：US882676
申请日：1986-07-07
申请人： Kazuhiko Honjo
发明人： Kazuhiko Honjo
IPC分类号： H01L27/095 , H01L21/338 , H01L21/8232 , H01L27/00 , H01L27/06 , H01L29/205 , H01L29/808 , H01L29/812 , H01L27/02 , H01L29/12 , H01L29/80
CPC分类号： H01L29/205 , H01L27/0605 , H01L29/808
摘要： In order to minimize the interconnections, there is provided a three-dimensional integrated circuit fabricated on a semi-insulating substrate of compound semiconductor material comprising a first compound semiconductor layer formed on the surface of the semi-insulating substrate and electrically connected to a variable voltage source, a second compound semiconductor layer formed on the surface of the first compound semiconductor layer opposite in conductivity type thereto and providing an electric device together with the first compound semiconductor layer, an undoped compound semiconductor layer epitaxially grown on the surface of the second compound semiconductor layer and formed with a plurality of doped regions for providing interconnections of the three dimensional integrated circuit, one of the interconnections providing an electric connections to the electric device formed with the first and second compound semiconductor layers, a doped compound semiconductor layer formed on the surface of the undoped compound semiconductor layer and capable of providing a current path established therein, and a conductive layer formed on the surface of the doped compound semiconductor layer and providing a gate to control the current path in the doped compound semiconductor layer, the conductive layer and the doped compound semiconductor layer forming parts of a field effect transistor which in turn forms parts of the three-dimensional integrated circuit together with the electric device.
摘要翻译：为了最小化互连，提供了一种制造在化合物半导体材料的半绝缘衬底上的三维集成电路，其包括形成在半绝缘衬底的表面上并电连接到可变电压的第一化合物半导体层源，形成在与导电类型相反的第一化合物半导体层的表面上并与第一化合物半导体层一起提供电子器件的第二化合物半导体层，外延生长在第二化合物半导体的表面上的未掺杂的化合物半导体层并且形成有多个用于提供三维集成电路的互连的掺杂区域，所述互连中的一个提供与形成有第一和第二化合物半导体层的电子器件的电连接，形成在第一和第二化合物半导体层上的掺杂化合物半导体层未掺杂的化合物半导体层的表面，并且能够提供其中建立的电流路径，以及形成在掺杂化合物半导体层的表面上并提供栅极以控制掺杂化合物半导体层中的电流路径的导电层，导电层并且掺杂的化合物半导体层形成场效应晶体管的一部分，该场效应晶体管又与电子器件一起形成三维集成电路的一部分。

50. 发明授权

US4576700A Perpendicular magnetic recording medium method for producing the same, and sputtering device 失效
标题翻译：垂直磁记录介质的制造方法及溅射装置
公开(公告)号：US4576700A
公开(公告)日：1986-03-18
申请号：US466863
申请日：1983-02-16
申请人： Sadao Kadokura , Kazuhiko Honjo , Takashi Tomie , Masahiko Naoe
发明人： Sadao Kadokura , Kazuhiko Honjo , Takashi Tomie , Masahiko Naoe
IPC分类号： C23C14/34 , G11B5/64 , G11B5/66 , G11B5/667 , G11B5/706 , G11B5/73 , G11B5/85 , G11B5/851 , H01F10/08 , H01F10/12 , H01F10/13 , H01F10/26 , H01F41/14 , G11B5/46
CPC分类号： G11B5/851 , G11B5/66
摘要： A magnetic recording medium conventionally utilizes the in-plane magnetization mode, but recently the perpendicular magnetization mode utilizing the perpendicular anisotropy of an hcp cobalt alloy layer, in which the C axis is oriented perpendicular to the layer surface, has been proposed. The known perpendicular magnetic recording medium is produced by means of RF sputtering and comprises a Permalloy layer, as layer of a low coercive-force material, between the nonmagnetic base and the hcp cobalt alloy layer. The perpendicular anisotropy attained by the present invention in very excellent and is superior to that of a perpendicular recording medium having no Permalloy layer because a Co-Ta alloy is used as the layer of a low coercive-force material.
摘要翻译：磁记录介质通常使用平面内磁化模式，但是最近提出了利用垂直于层表面C轴定向的hcp钴合金层的垂直各向异性的垂直磁化模式。已知的垂直磁记录介质通过RF溅射制造，并且在非磁性基底和hcp钴合金层之间包括作为低矫顽力材料层的坡莫合金层。由于使用Co-Ta合金作为低矫顽力材料层，本发明获得的垂直各向异性非常优异并优于不具有坡莫合金层的垂直记录介质。

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