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41. 发明申请

US20050208701A1 Semiconductor chip packaging method with individually placed film adhesive pieces 有权
标题翻译：半导体芯片封装方法，单独放置薄膜胶片
公开(公告)号：US20050208701A1
公开(公告)日：2005-09-22
申请号：US10976601
申请日：2004-10-29
申请人： Jin-Wook Jeong , In-Sang Yoon , Hee Lee , Hyun-Joon Oh , Hyeog Kwon , Jong Ju , Sang Lee
发明人： Jin-Wook Jeong , In-Sang Yoon , Hee Lee , Hyun-Joon Oh , Hyeog Kwon , Jong Ju , Sang Lee
IPC分类号： H01L21/44 , H01L21/58 , H01L21/68 , H01L21/98 , H01L23/31 , H01L23/49 , H01L25/065
CPC分类号： H01L24/27 , H01L21/6835 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2224/8385 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06555 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： Individual pieces of film adhesive (42) are placed on a support surface (46). Diced semiconductor chips (24) are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (52). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (54), to create second chip subassemblies ((56). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (58), to create semiconductor chip packages (60).
摘要翻译：单个薄膜粘合剂片（42）被放置在支撑表面（46）上。切割的半导体芯片（24）被分别放置在薄膜粘合剂的各个片上，从而将切割的半导体芯片固定到支撑表面以形成第一芯片组件（52）。多个第一芯片子组件中的每一个的切割半导体芯片和支撑表面电连接，例如通过导线（54），以形成第二芯片子组件（56），至少部分第二芯片组件诸如用模制化合物（58）封装芯片组件以产生半导体芯片封装（60）。

42. 发明申请

US20050185467A1 Method of erasing a flash memory cell 有权
标题翻译：擦除闪存单元的方法
公开(公告)号：US20050185467A1
公开(公告)日：2005-08-25
申请号：US11118858
申请日：2005-04-29
申请人： Hee Lee
发明人： Hee Lee
IPC分类号： H01L21/8247 , G11C16/14 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C11/14 , G11C16/14 , G11C16/16
摘要： Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.
摘要翻译：公开了一种用于擦除闪存单元的方法，包括：（a）半导体衬底，（b）栅极，（c）源极，（d）漏极（e）阱，所述栅极包括：（1）隧道氧化膜，（2）浮栅，（3）电介质膜和（4）堆叠在半导体衬底上的控制栅。在所公开的方法之一中，将负偏置电压施加到控制栅极，源极和漏极浮置，向阱施加正偏置电压，从而在源极和漏极中产生正偏压，接地第一时间向阱施加电压，同时将负偏置电压保持为控制栅极; 然后将接地电压施加到控制栅极。

43. 发明申请

US20050133853A1 Flash memory cell and method of erasing the same 审中-公开
标题翻译：闪存单元和擦除方法相同
公开(公告)号：US20050133853A1
公开(公告)日：2005-06-23
申请号：US10881423
申请日：2004-06-30
申请人： Hee Lee
发明人： Hee Lee
IPC分类号： G11C16/02 , G11C11/34 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/16
摘要： Provided is related to a flash memory cell and method of erasing the same. A P-type well field-effective flash cell is comprised of a drain formed in a P-type semiconductor substrate, a channel region made of a triple N-well, a source of P-well formed in the triple N-well, a floating gate formed on the channel region, a tunnel oxide film formed under the floating gate, a control gate formed with a predetermined pattern on the overall structure including the floating gate, and a dielectric film formed under the control gate. When the flash cell is turned on at a predetermined threshold voltage to drop a P-well bias, an electric field between the floating gate and the semiconductor substrate weakens to inhibit electron injection that is caused by F-N tunneling effect and thereby an erased threshold voltage goes to a target voltage.
摘要翻译：提供了一种闪存单元及其擦除方法。 P型阱场有效闪存单元由在P型半导体衬底中形成的漏极，由三重N阱构成的沟道区，在三重N阱中形成的P阱的源，形成在沟道区上的浮置栅极，形成在浮置栅极下方的隧道氧化物膜，在包括浮置栅极的整个结构上形成具有预定图案的控制栅极以及形成在控制栅极下的电介质膜。当闪光单元在预定阈值电压下接通以降低P阱偏压时，浮置栅极和半导体衬底之间的电场减弱，以抑制由FN隧穿效应引起的电子注入，从而消除阈值电压达到目标电压。

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