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41. 发明授权

US6104056A Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US6104056A
公开(公告)日：2000-08-15
申请号：US126437
申请日：1998-07-30
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L21/8247 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/28 , H01L21/336 , H01L27/01 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/036 , H01L31/062 , H01L31/112 , H01L31/113 , H01L21/119
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/7888 , G11C2216/06 , G11C2216/08 , H01L27/1203 , H01L29/785
摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.
摘要翻译：一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。根据一个实施例，提供了从沟道分离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

42. 发明授权

US6072354A Semiconductor device output buffer circuit for LSI 失效
标题翻译： LSI半导体器件输出缓冲电路
公开(公告)号：US6072354A
公开(公告)日：2000-06-06
申请号：US939334
申请日：1997-09-29
申请人： Toshikazu Tachibana , Takeshi Sakai , Yoshinobu Nakagome
发明人： Toshikazu Tachibana , Takeshi Sakai , Yoshinobu Nakagome
IPC分类号： H03K19/017 , H03K17/16
CPC分类号： H03K19/01714 , Y10T307/438
摘要： In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.
摘要翻译：在具有诸如半导体存储器件的多个输出电路的半导体器件中，将由升压电路产生的升压电压电平的驱动信号施加到输出电路中的低电平输出MOS晶体管的栅极。结果，即使在接地布线的电位浮起时，也可以防止接地布线和低电平输出MOS晶体管的栅极之间的电位差的显着降低。此外，具有足够高电平的信号可以被提供给低电平输出输出MOS晶体管的栅极。结果，可以抑制输出MOS晶体管的开关操作的延迟，并且输出电路可以高速运行。

43. 发明授权

US5677880A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5677880A
公开(公告)日：1997-10-14
申请号：US407850
申请日：1995-03-21
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

44. 发明授权

US5600163A Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US5600163A
公开(公告)日：1997-02-04
申请号：US291752
申请日：1994-08-16
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L21/8247 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/28 , H01L21/336 , H01L27/01 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/036 , H01L31/062 , H01L31/112 , H01L31/113
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/7888 , G11C2216/06 , G11C2216/08 , H01L27/1203 , H01L29/785
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

45. 发明授权

US5455797A Reference voltage generator 失效
标题翻译：参考电压发生器
公开(公告)号：US5455797A
公开(公告)日：1995-10-03
申请号：US317736
申请日：1994-10-04
申请人： Jun Etoh , Yoshinobu Nakagome , Hitoshi Tanaka , Koji Kawamoto , Masakazu Aoki
发明人： Jun Etoh , Yoshinobu Nakagome , Hitoshi Tanaka , Koji Kawamoto , Masakazu Aoki
IPC分类号： G05F3/24 , G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G05F3/24 , G11C11/4074 , G11C5/147
摘要： An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.
摘要翻译：一种装置，包括用于基于两个MOS晶体管的阈值电压之间的差产生电压的恒压发生器和用于对恒压发生器电路的输出电压进行采样的电压采样装置，其中，电压采样装置对用于恒压发生器的电源开关之前的恒压发生器被关断。

46. 发明授权

US4994688A Semiconductor device having a reference voltage generating circuit 失效
标题翻译：具有基准电压发生电路的半导体装置
公开(公告)号：US4994688A
公开(公告)日：1991-02-19
申请号：US323966
申请日：1989-03-15
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203 , Y10S323/907
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

47. 发明授权

US4661929A Semiconductor memory having multiple level storage structure 失效
标题翻译：具有多级存储结构的半导体存储器
公开(公告)号：US4661929A
公开(公告)日：1987-04-28
申请号：US686018
申请日：1984-12-24
申请人： Masakazu Aoki , Yoshinobu Nakagome , Masashi Horiguchi , Shinichi Ikenaga , Katsuhiro Shimohigashi
发明人： Masakazu Aoki , Yoshinobu Nakagome , Masashi Horiguchi , Shinichi Ikenaga , Katsuhiro Shimohigashi
IPC分类号： G06F11/10 , G11C7/06 , G11C11/4091 , G11C11/56 , G11C11/40
CPC分类号： G11C11/565 , G11C11/4091 , G11C7/065 , G06F11/1072 , G11C29/00 , G11C7/06
摘要： In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.
摘要翻译：在半导体存储器中，包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列，指定每个存储单元的位置的寻址电路，发送连接到所述存储单元的数据的数据线和数据写入和读取电路连接到所述数据线。半导体存储器具有多级存储结构。具体而言，该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置，作为所述数据读取电路的偏置电荷供给装置以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

48. 发明申请

US20080061298A1 SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：半导体元件和半导体存储器件使用它
公开(公告)号：US20080061298A1
公开(公告)日：2008-03-13
申请号：US11931369
申请日：2007-10-31
申请人： Kazuo YANO , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo YANO , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/04 , H01L29/78
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/40114 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second insulator films sandwich the first region and a first gate electrode is connected to the first region through the first insulator film. In this arrangement, the first region is adapted to accumulate charges corresponding to stored information.
摘要翻译：半导体存储器件包括多个存储器单元，每个存储单元包括由半导体材料形成的源极区域，由半导体材料形成的漏极区域和由半导体材料形成并位于源极区域和漏极之间的第一区域地区。第一和第二绝缘膜夹着第一区域，第一栅电极通过第一绝缘膜连接到第一区域。在这种布置中，第一区域适于累积对应于存储的信息的费用。

49. 发明申请

US20060208315A1 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US20060208315A1
公开(公告)日：2006-09-21
申请号：US11439152
申请日：2006-05-24
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

50. 发明授权

US06680875B2 Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption 有权
标题翻译：诸如同步DRAM的半导体器件，包括用于降低功耗的控制电路
公开(公告)号：US06680875B2
公开(公告)日：2004-01-20
申请号：US10259579
申请日：2002-09-30
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.
摘要翻译：一种半导体器件，包括多个存储体和对应于存储体的多个电源电路。每个存储体被激活命令独立地激活。给定外部提供的电压，每个电源电路输出预定的内部电源电压。每个电源电路的输出连接到相应的存储体。响应于用于激活存储体之一的命令，相应的电源电路被激活，而剩余的电源电路被去激活。

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