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41. 发明授权

US07316952B2 Method for forming a memory device with a recessed gate 有权
标题翻译：用于形成具有凹入栅极的存储器件的方法
公开(公告)号：US07316952B2
公开(公告)日：2008-01-08
申请号：US11141656
申请日：2005-05-31
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10891
摘要： A method for forming a semiconductor device. A substrate, having a plurality of deep trench capacitors therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded by the deep trench capacitor devices. The predetermined region of the substrate is etched using the spacers and the upper portions of the deep trench capacitors serve as a mask to form a recess, and a recessed gate is formed in the recess.
摘要翻译：一种形成半导体器件的方法。提供了其中具有多个深沟槽电容器的衬底，其中露出了深沟槽电容器器件的上部。形成深沟槽电容器的上部侧壁上的间隔，以形成由深沟槽电容器器件包围的预定区域。使用间隔物蚀刻衬底的预定区域，并且深沟槽电容器的上部用作掩模以形成凹部，并且在凹部中形成凹入栅极。

42. 发明申请

US20070138545A1 Semiconductor device having a trench gate and method of fabricating the same 有权
标题翻译：具有沟槽栅的半导体器件及其制造方法
公开(公告)号：US20070138545A1
公开(公告)日：2007-06-21
申请号：US11491704
申请日：2006-07-24
申请人： Jeng-Ping Lin , Pei-Ing Lee
发明人： Jeng-Ping Lin , Pei-Ing Lee
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7834 , H01L27/10876 , H01L29/42368 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.
摘要翻译：提供一种制造具有沟槽栅极的半导体器件的方法。首先，提供其上具有沟槽蚀刻掩模的半导体衬底。蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。栅极绝缘层形成在第二沟槽的侧壁和底部上。沟槽栅极形成在第二沟槽中。

43. 发明申请

US20070032085A1 METHOD FOR FORMING RECESSES 有权
标题翻译：形成记忆的方法
公开(公告)号：US20070032085A1
公开(公告)日：2007-02-08
申请号：US11195293
申请日：2005-08-02
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/3086 , H01L21/26586 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/66621 , Y10S438/944 , Y10S438/947
摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.
摘要翻译：一种形成凹部的方法。该方法包括提供具有两个突出物的两个突起，所述两个突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上共形成掩模层和突起，倾斜地将掩模层以第一使用与突起的第一侧壁相邻的第一注入掩模的角度，使用与突起的第二侧壁相邻的第二注入掩模以第二角度注入掩模层，去除掩模层的植入部分以形成图案化掩模层，并使用图案化掩模层蚀刻基板，从而形成凹部，其中分别从凹部到两个突起的距离不同。

44. 发明申请

US20070032038A1 Method for forming recesses 有权
标题翻译：凹槽形成方法
公开(公告)号：US20070032038A1
公开(公告)日：2007-02-08
申请号：US11195294
申请日：2005-08-02
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/76
CPC分类号： H01L21/3086 , H01L21/26586 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/66621 , Y10S438/944 , Y10S438/947
摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.
摘要翻译：一种形成凹部的方法。该方法包括提供具有两个突起的基底，该突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上保形地形成掩模层和突起，使用第一将掩模与所述突起的第一侧壁相邻地植入，去除所述掩模层的注入部分以形成图案化掩模层，并且使用所述图案化掩模层蚀刻所述衬底，从而形成凹部。

45. 发明授权

US07005698B2 Split gate flash memory cell 有权
标题翻译：分闸门闪存单元
公开(公告)号：US07005698B2
公开(公告)日：2006-02-28
申请号：US10668902
申请日：2003-09-23
申请人： Chi-Hui Lin , Jeng-Ping Lin , Pei-Ing Lee , Jih-Chang Lien
发明人： Chi-Hui Lin , Jeng-Ping Lin , Pei-Ing Lee , Jih-Chang Lien
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11553 , H01L29/42324 , H01L29/7885
摘要： A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.
摘要翻译：分闸门闪存单元。存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。导线设置在衬底的沟槽的下部。源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。绝缘支柱设置在绝缘层上。第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。漏极区域形成在与第一导电层相邻的衬底中。

46. 发明授权

US6100117A Method for manufacturing DRAM having a redundancy circuit region 失效
标题翻译：一种用于制造具有冗余电路区域的DRAM的方法
公开(公告)号：US6100117A
公开(公告)日：2000-08-08
申请号：US62639
申请日：1998-04-20
申请人： Chung Peng Hao , Chung Lin Huang , Lee Chung Yuan , Pei-Ing Lee , Wu Hsiung Chen
发明人： Chung Peng Hao , Chung Lin Huang , Lee Chung Yuan , Pei-Ing Lee , Wu Hsiung Chen
IPC分类号： H01L21/8242 , H01L23/525 , H01L27/108 , H01L21/82
CPC分类号： H01L27/10894 , H01L23/5258 , H01L27/10897 , H01L2924/0002
摘要： A method for manufacturing DRAM having a redundancy circuit region. The method utilizes a laser beam permeable layer such as a silicon nitride layer to serve as a stop layer in the etching step of the passivation oxide layer. The method removes the conductive layer, serving as the upper electrode of the capacitor, in the redundancy circuit region II. The fuse of the redundancy circuit region II can thereby be easily blown by the laser beam.
摘要翻译：一种用于制造具有冗余电路区域的DRAM的方法。该方法在钝化氧化物层的蚀刻步骤中利用诸如氮化硅层的激光束可透过层作为停止层。该方法在冗余电路区域II中去除用作电容器的上电极的导电层。因此，冗余电路区域II的熔断体可以容易地被激光束吹制。

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