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41. 发明授权

US08664632B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08664632B2
公开(公告)日：2014-03-04
申请号：US13599504
申请日：2012-08-30
申请人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
发明人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： H01L45/1253 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
摘要翻译：根据一个实施例，存储器件包括第一电极，第二电极和可变电阻膜。可变电阻膜连接在第一电极和第二电极之间。第一电极包括由导电材料制成的基体中所含的金属。金属的内聚能低于导电材料的内聚能。第一电极的宽度方向的中央部的金属浓度高于第一电极的宽度方向的两端部的金属的浓度。

42. 发明申请

US20130307054A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20130307054A1
公开(公告)日：2013-11-21
申请号：US13606292
申请日：2012-09-07
申请人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
IPC分类号： H01L27/105
CPC分类号： G11C16/10 , H01L21/823456 , H01L21/823462 , H01L27/11526 , H01L27/11573 , H01L29/7881 , H01L29/792
摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.
摘要翻译：一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

43. 发明申请

US20130250656A1 RESISTANCE-VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变存储器件
公开(公告)号：US20130250656A1
公开(公告)日：2013-09-26
申请号：US13605746
申请日：2012-09-06
申请人： Takayuki ISHIKAWA , Yoshifumi Nishi , Daisuke Matsushita , Masato Koyama
发明人： Takayuki ISHIKAWA , Yoshifumi Nishi , Daisuke Matsushita , Masato Koyama
IPC分类号： H01L45/00 , G11C11/21
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/145
摘要： A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.
摘要翻译：存储器件包括第一电极，第二电极，第三电极，第一电极和第三电极之间的第一可变电阻层，以及在第二电极和第三电极之间的第二可变电阻层。第一，第二和第三电极以及第一和第二可变电阻层由当第一和第二电极层施加电压时使第一可变电阻层从高电阻状态转变为低电阻状态的材料形成电极，当电压被切断时保持高电阻状态，并且当电压施加在第一和第二电极两端并从高电阻转变时，使第二可变电阻层从高电阻状态转变到低电阻状态当电压被切断时，状态为低电阻状态。

44. 发明授权

US08525251B2 Nonvolatile programmable logic switch 失效
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08525251B2
公开(公告)日：2013-09-03
申请号：US13221292
申请日：2011-08-30
申请人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
发明人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

45. 发明授权

US07977182B2 Method of manufacturing MISFET with low contact resistance 失效
标题翻译：具有低接触电阻的MISFET的制造方法
公开(公告)号：US07977182B2
公开(公告)日：2011-07-12
申请号：US12323770
申请日：2008-11-26
申请人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
发明人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
IPC分类号： H01L21/8238 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译：这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。第二金属沉积在金属半导体化合物层上。通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

46. 发明授权

US07028645B2 Pilot oil ignition gas engine and method of operating pilot oil ignition gas engine 失效
公开(公告)号：US07028645B2
公开(公告)日：2006-04-18
申请号：US10415046
申请日：2002-08-29
申请人： Satoru Goto , Yoshifumi Nishi
发明人： Satoru Goto , Yoshifumi Nishi
IPC分类号： F02B3/00
CPC分类号： F02M43/00 , F02D19/061 , F02D19/10 , F02D41/0027 , F02D41/042 , Y02T10/36
摘要： The gas engine of the present invention has a pilot oil fuel valve, a pilot oil pump, and first and second pipes connected to a pilot oil main pipe, for each of a plurality of combustion chambers. An operating pilot oil tank and an ignition stimulant-added pilot oil tank are connected via a switching valve to a third pipe, connected to an end of the pilot oil main pipe. Before operating stops, the pilot oil is discharged by opening an exhaust valve, and thereafter, the switching valve is switched and pilot oil which the ignition stimulant has been added to is supplied into the pipe. Consequently, the pilot oil downstream from the main pipe is replaced with the pilot oil which the ignition stimulant has been added to. Therefore, at the time of the next activation, pilot oil which the ignition stimulant has been added to is sprayed from the fuel valve, and, as a result, misfire at the time of activation is reduced, and a highly reliable engine is obtained.

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