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41. 发明授权

US09183138B2 Encoding program data based on data stored in memory cells to be programmed 有权
标题翻译：根据存储在要编程的存储单元中的数据编码程序数据
公开(公告)号：US09183138B2
公开(公告)日：2015-11-10
申请号：US14053893
申请日：2013-10-15
申请人： Younggeon Yoo , Junjin Kong , Changkyu Seol , Hong Rak Son , Hyunseuk Yoo
发明人： Younggeon Yoo , Junjin Kong , Changkyu Seol , Hong Rak Son , Hyunseuk Yoo
IPC分类号： G06F12/02 , G11C16/10 , G11C13/00
CPC分类号： G06F12/0246 , G11C11/1659 , G11C11/1675 , G11C13/0069 , G11C16/10 , G11C2013/0076
摘要： A method of programming data in a nonvolatile memory device comprises receiving program data to be programmed in selected memory cells of the nonvolatile memory device, reading data from the selected memory cells, encoding the program data using at least one encoding scheme selected from among multiple encoding schemes according to a comparison of the program data and the read data, generating flag data including encoding information, and programming the encoded program data and the flag data in the selected memory cells.
摘要翻译：一种在非易失性存储器件中编程数据的方法包括：接收要在非易失性存储器件的选定存储器单元中编程的程序数据，从所选择的存储器单元读取数据，使用从多个编码中选择的至少一种编码方案对程序数据进行编码根据程序数据和读取数据的比较，生成包括编码信息的标志数据，以及对选择的存储单元中的编码程序数据和标志数据进行编程的方案。

42. 发明授权

US09111626B2 Semiconductor memory systems using regression analysis and read methods thereof 有权
标题翻译：使用回归分析及其读取方法的半导体存储器系统
公开(公告)号：US09111626B2
公开(公告)日：2015-08-18
申请号：US14062092
申请日：2013-10-24
申请人： Kwanghoon Kim , Junjin Kong , Changkyu Seol , Hong Rak Son
发明人： Kwanghoon Kim , Junjin Kong , Changkyu Seol , Hong Rak Son
IPC分类号： G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34 , G11C16/10
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3422 , G11C16/349
摘要： A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
摘要翻译：存储器系统包括：位计数器和回归分析器。位计数器被配置为基于使用多个不同的读取电压从所选择的存储器单元读取的数据生成多个计数值，多个计数值中的每一个表示具有阈值电压的存储器件的存储单元的数量在多个不同读取电压的对之间。回归分析器被配置为使用回归分析来基于多个计数值来确定所选择的存储器单元的读取电压。

43. 发明申请

US20120257455A1 NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES 有权
标题翻译：非易失性存储器件和操作非易失性存储器件的方法
公开(公告)号：US20120257455A1
公开(公告)日：2012-10-11
申请号：US13211743
申请日：2011-08-17
申请人： Eun Chu Oh , Hong Rak Son , KyoungLae Cho , Junjin Kong
发明人： Eun Chu Oh , Hong Rak Son , KyoungLae Cho , Junjin Kong
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.
摘要翻译：操作包括多个单元串的非易失性存储器件的方法，每个单元串具有至少一个接地选择晶体管，多个存储单元和至少一个串选择晶体管，所述操作方法包括接收命令和地址，确定施加的电压响应于输入命令和地址的时间，以及在确定的电压施加时间期间，将特定电压施加到对应于输入地址的单元串的存储单元。

44. 发明申请

US20110289384A1 MEMORY SYSTEM WITH PAGE-BASED ITERATIVE DECODING STRUCTURE AND PAGE-BASED ITERATIVE DECODING METHOD THEREOF 有权
标题翻译：具有基于页面的迭代解码结构的存储器系统和基于页面的迭代解码方法
公开(公告)号：US20110289384A1
公开(公告)日：2011-11-24
申请号：US13110395
申请日：2011-05-18
申请人： Kijun Lee , Hong Rak Son , Junjin Kong
发明人： Kijun Lee , Hong Rak Son , Junjin Kong
IPC分类号： H03M13/05 , G06F11/10 , G06F12/00
CPC分类号： H03M13/2951 , G06F11/1008 , H03M13/2948
摘要： A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.
摘要翻译：提供了一种迭代地解码通过信道传送的数据的方法。该方法可以包括以连续顺序迭代地解码数据的1至N个扇区的每个扇区，直到所有N个扇区被解码，其中在确定对应于N个扇区的当前扇区的迭代解码的成功完成时，立即启动迭代解码 N部门的下一个部门。

45. 发明授权

US06968495B2 Super high speed viterbi decoder using circularly connected 2-dimensional analog processing cell array 失效
标题翻译：超高速维特比解码器采用循环连接的二维模拟处理单元阵列
公开(公告)号：US06968495B2
公开(公告)日：2005-11-22
申请号：US10175034
申请日：2002-06-20
申请人： Hong Rak Son , Young Su Park
发明人： Hong Rak Son , Young Su Park
IPC分类号： H03M13/41 , H03M13/03
CPC分类号： H03M13/6505 , H03M13/3961 , H03M13/41
摘要： A super high speed Viterbi decoder and decoding method with a circularly connected 2-dimensional analog processing cell array. The Viterbi decoder has a 2-dimensional parallel processing structure, in which analog processing cells are located at nodes of a trellis diagram. An output column of the analog processing cells is connected to a decoding column. Thus, the output column becomes a column right before the decoding column. A reference input signal given at a decoding column is propagated to the whole network, while its magnitude is reduced by an amount of an error metric on each branch. The circuit-based decoding is done by adding trigger signals to disconnect the path corresponding to logic 0 (or 1), and by observing its effect at the output column.
摘要翻译：具有循环连接的2维模拟处理单元阵列的超高速维特比解码器和解码方法。维特比解码器具有二维并行处理结构，其中模拟处理单元位于格子图的节点处。模拟处理单元的输出列连接到解码列。因此，输出列成为解码列之前的列。在解码列处给出的参考输入信号被传播到整个网络，而其幅度减小每个分支上的误差度量的量。基于电路的解码是通过添加触发信号来断开与逻辑0（或1）相对应的路径，并通过观察其在输出列的效应来完成的。

46. 发明授权

US10013211B2 Storage devices including nonvolatile memory devices and access methods for nonvolatile memory devices 有权
公开(公告)号：US10013211B2
公开(公告)日：2018-07-03
申请号：US15605404
申请日：2017-05-25
申请人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
发明人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
IPC分类号： G11C7/00 , G06F3/06 , G06N99/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0619 , G06F3/0656 , G06F3/0679 , G06N20/00 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

47. 发明授权

US09437310B2 Method of operating a memory system having an erase control unit 有权
标题翻译：一种具有擦除控制单元的存储系统的操作方法
公开(公告)号：US09437310B2
公开(公告)日：2016-09-06
申请号：US14827930
申请日：2015-08-17
申请人： Eun Chu Oh , Hong Rak Son , Junjin Kong
发明人： Eun Chu Oh , Hong Rak Son , Junjin Kong
IPC分类号： G11C16/10 , G11C16/16 , G11C11/56 , G11C16/34 , G11C16/26
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/26 , G11C16/3468
摘要： A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition.
摘要翻译：一种操作包括包括存储器块的非易失性存储器的存储器系统的方法和包括擦除控制单元的存储器控制器，包括执行预读取连接到所述存储器块的选定字线的多个存储器单元，产生关断基于预读取结果的单元计数，通过擦除控制单元的操作，将关闭单元计数与参考值进行比较以产生比较结果，以及通过非易失性存储器的操作来改变基于比较结果的擦除操作条件存储器，并根据改变的擦除操作条件擦除存储器块。

48. 发明授权

US09093145B2 Non-volatile random access memory device and data read method thereof 有权
标题翻译：非易失性随机存取存储器件及其数据读取方法
公开(公告)号：US09093145B2
公开(公告)日：2015-07-28
申请号：US14141609
申请日：2013-12-27
申请人： Eun Chu Oh , JunJin Kong , Hong Rak Son , Younggeon Yoo
发明人： Eun Chu Oh , JunJin Kong , Hong Rak Son , Younggeon Yoo
IPC分类号： G11C7/00 , G11C13/00
CPC分类号： G11C13/004 , G11C11/16 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C2013/0054
摘要： A nonvolatile random access memory device includes a plurality of memory cells configured to store data therein, a plurality of reference cells separate from the memory cells, the reference cells each configured to output a corresponding reference cell signal, and a read/write circuit. The read/write circuit is configured to generate from the reference cell signals a reference signal which is variable to have a plurality of different reference levels. The read/write circuit is further configured to identify, in response to the reference signal, a logic state among a first logic state and a second logic state for each of one or more selected memory cells, and to output read data corresponding to the identified logic state.
摘要翻译：非易失性随机存取存储器件包括多个存储器单元，其被配置为在其中存储数据，多个参考单元与存储器单元分离，每个参考单元被配置为输出相应的参考单元信号，以及读/写电路。读/写电路被配置为从参考单元信号产生可变为具有多个不同参考电平的参考信号。读/写电路还被配置为响应于参考信号识别一个或多个所选择的存储器单元中的每一个的第一逻辑状态和第二逻辑状态之间的逻辑状态，并且输出与所识别的对应的读取数据逻辑状态。

49. 发明授权

US08516183B2 Method of estimating read level for a memory device, memory controller therefor, and recording medium 失效
标题翻译：用于估计存储器件，其存储器控制器和记录介质的读取电平的方法
公开(公告)号：US08516183B2
公开(公告)日：2013-08-20
申请号：US13114337
申请日：2011-05-24
申请人： Hee Seok Eun , Hong Rak Son , Jong Ha Kim , Young June Kim , Seong Hyeog Choi
发明人： Hee Seok Eun , Hong Rak Son , Jong Ha Kim , Young June Kim , Seong Hyeog Choi
IPC分类号： G06F12/00
CPC分类号： G11C11/5642 , G06F12/0246 , G06F2212/7209 , G11C16/3404 , G11C16/349
摘要： A method of estimating a read level for a memory device includes calculating first information corresponding to at least one among information about the number of cells having a particular logic level in data to be programmed and information about the number of cells having a particular cell state and storing the first information during a program operation; reading the data based on a threshold level that has been set and calculating second information about the number of cells in at least one state defined by the threshold level with respect to the read data; calculating third information about the number of cells in the at least one state, which corresponds to the second information, using a probability based on the first information; comparing the second information with the third information; and determining whether to change the threshold level according to the comparison result.
摘要翻译：一种估计存储器件的读取电平的方法包括：计算对应于关于要编程的数据中具有特定逻辑电平的单元的数量的信息中的至少一个的信息的第一信息以及关于具有特定单元状态的单元的数量的信息，以及在程序操作期间存储第一信息; 基于已经设置的阈值水平读取数据，并且相对于读取的数据计算关于由阈值水平定义的至少一个状态中的单元数量的第二信息; 使用基于所述第一信息的概率来计算与所述第二信息对应的所述至少一个状态下的小区的数量的第三信息; 将第二信息与第三信息进行比较; 以及根据比较结果确定是否改变阈值水平。

50. 发明申请

US20180067697A1 Storage Devices Including Nonvolatile Memory Devices and Access Methods for Nonvolatile Memory Devices 有权
公开(公告)号：US20180067697A1
公开(公告)日：2018-03-08
申请号：US15605404
申请日：2017-05-25
申请人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
发明人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
IPC分类号： G06F3/06 , G06N99/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06N99/005 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

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