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41. 发明申请

US20120292735A1 CORNER TRANSISTOR SUPPRESSION 审中-公开
标题翻译：角膜晶体管抑制
公开(公告)号：US20120292735A1
公开(公告)日：2012-11-22
申请号：US13112317
申请日：2011-05-20
申请人： Shyue Seng (Jason) Tan , Ying Keung Leung , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Ying Keung Leung , Elgin Quek
IPC分类号： H01L29/06 , H01L29/68 , H01L21/31
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/088
摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
摘要翻译：形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。

42. 发明申请

US20120223318A1 P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION 有权
标题翻译：带增强带对带隧道热电子注射的P通道闪光
公开(公告)号：US20120223318A1
公开(公告)日：2012-09-06
申请号：US13038081
申请日：2011-03-01
申请人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
发明人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513
摘要： A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.
摘要翻译：形成p沟道闪速存储器，其中嵌入有形成有升高的源极/漏极的异质结层中的电荷存储堆叠。实施例包括在衬底上形成虚拟栅极堆叠，通过选择性外延生长在虚设栅极堆叠的每一侧上在衬底上形成层，在层上形成间隔物，形成升高的源极/漏极，去除虚拟栅极堆叠，形成间隔件之间的空腔，并且在空腔中形成存储器栅极堆叠。不同的实施例包括形成窄带隙材料的层，在间隔物下方的窄带隙层和与其相邻的宽带隙层，或在间隔物下方的宽带隙层，与其相邻的窄带隙层，以及宽带隙层窄带隙层。

43. 发明授权

US09362274B2 Self-aligned contact for replacement metal gate and silicide last processes 有权
公开(公告)号：US09362274B2
公开(公告)日：2016-06-07
申请号：US13867684
申请日：2013-04-22
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76 , H01L27/088 , H01L21/8234 , H01L21/768 , H01L21/285 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

44. 发明授权

US09064803B2 Split-gate flash memory exhibiting reduced interference 有权
标题翻译：分离式闪存表现出减小的干扰
公开(公告)号：US09064803B2
公开(公告)日：2015-06-23
申请号：US13189964
申请日：2011-07-25
申请人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
IPC分类号： H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11517 , H01L21/28273 , H01L29/42328 , H01L29/513
摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
摘要翻译：分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。实施例包括具有包含低k和高k层的电介质间隔物的存储单元。其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

45. 发明授权

US08946806B2 Memory cell with decoupled channels 有权
标题翻译：具有解耦通道的存储单元
公开(公告)号：US08946806B2
公开(公告)日：2015-02-03
申请号：US13189554
申请日：2011-07-24
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek , Yanzhe Tang
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek , Yanzhe Tang
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11568 , G11C16/04 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11526 , H01L27/11573 , H01L29/42324 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/7883
摘要： A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
摘要翻译：公开了一种具有由具有存储单元的存储单元区制备的衬底的器件。存储单元包括存取晶体管和存储晶体管。存取晶体管包括第一和第二源极/漏极（S / D）区域，并且存储晶体管包括第一和第二存储S / D区域。访问和存储晶体管串联耦合，第二S / D区域是公共S / D区域。擦除栅极设置在公共S / D区域上。在第一存储S / D区域上设置有编程门。存储器单元的这种布置使程序通道和擦除通道分离。

46. 发明申请

US20140070159A1 NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR 有权
标题翻译：基于SI的选择器的STI新型RRAM结构
公开(公告)号：US20140070159A1
公开(公告)日：2014-03-13
申请号：US13611817
申请日：2012-09-12
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2445 , H01L45/08 , H01L45/124 , H01L45/146 , H01L45/1683
摘要： An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
摘要翻译：公开了一种STI区域的RRAM，其具有垂直BJT选择器。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域底部周围和下方形成第一极性的阱，在STI区域的相对侧上的阱上具有第二极性的带，以及在基板的表面上的第二极性的每个带的第一极性的有源区域，在有源区上形成硬掩模，去除STI区域顶部以形成空腔，在腔侧和底表面上形成RRAM衬垫，在空腔中形成顶部电极，去除硬掩模的一部分以在空腔的相对侧上形成间隔物，以及将第二极性的掺杂剂注入远离空腔的每个有效区域的一部分。

47. 发明授权

US08119541B2 Modulation of stress in stress film through ion implantation and its application in stress memorization technique 有权
标题翻译：通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用
公开(公告)号：US08119541B2
公开(公告)日：2012-02-21
申请号：US12510276
申请日：2009-07-28
申请人： Lee Wee Teo , Elgin Quek
发明人： Lee Wee Teo , Elgin Quek
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/823864
摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.
摘要翻译：本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。对应力层进行重离子注入，然后进行退火。这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

48. 发明授权

US07998835B2 Strain-direct-on-insulator (SDOI) substrate and method of forming 有权
标题翻译：绝缘体绝缘体（SDOI）基板及其成型方法
公开(公告)号：US07998835B2
公开(公告)日：2011-08-16
申请号：US12008841
申请日：2008-01-15
申请人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
发明人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/165 , H01L21/76254 , H01L29/1054 , Y10S438/933
摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.
摘要翻译：描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。绝缘体邻近最外层应变硅层设置。最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

49. 发明授权

US07888214B2 Selective stress relaxation of contact etch stop layer through layout design 有权
标题翻译：通过布局设计，接触蚀刻停止层的选择性应力松弛
公开(公告)号：US07888214B2
公开(公告)日：2011-02-15
申请号：US11302035
申请日：2005-12-13
申请人： Lee Wee Teo , Elgin Quek , Dong Kyun Sohn
发明人： Lee Wee Teo , Elgin Quek , Dong Kyun Sohn
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76829 , H01L21/823814 , H01L21/823871 , H01L27/0207 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.
摘要翻译：一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

50. 发明申请

US20080150037A1 Selective STI Stress Relaxation Through Ion Implantation 有权
标题翻译：通过离子植入选择性STI应力松弛
公开(公告)号：US20080150037A1
公开(公告)日：2008-06-26
申请号：US11615980
申请日：2006-12-24
申请人： Lee Wee Teo , Shiang Yang Ong , Jae Gon Lee , Vincent Leong , Elgin Quek , Dong Kyun Sohn
发明人： Lee Wee Teo , Shiang Yang Ong , Jae Gon Lee , Vincent Leong , Elgin Quek , Dong Kyun Sohn
IPC分类号： H01L27/092 , H01L21/762 , H01L29/78 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/092 , H01L21/31155 , H01L21/76224 , H01L21/823807 , H01L29/6659 , H01L29/7846
摘要： A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.
摘要翻译：第一示例性实施例包括以下步骤和由其形成的结构。在衬底内形成具有相对侧壁的沟槽。在相对的沟槽侧壁上形成具有固有应力的应力层。应力层在沟槽侧壁上具有应力层侧壁。将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力的应力层部分被松弛。

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