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41. 发明授权

US08516182B2 Controller and memory system for managing data 失效
标题翻译：用于管理数据的控制器和存储器系统
公开(公告)号：US08516182B2
公开(公告)日：2013-08-20
申请号：US12554272
申请日：2009-09-04
申请人： Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7207 , G06F2212/7209
摘要： A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.
摘要翻译：控制器包括用于转换表的存储器，其中显示闪存中的逻辑和物理地址彼此对应; 指示存储在每个块中的每个页面中存储的数据的状态的FAT信息和每个识别由FAT信息指示的状态中存储有数据的页面所属的块的FAT信息标识符，同时保持它们相互对应; 另一个用于表示块标识符的块管理表的存储器，指示是否使用相应块的使用状态判断信息以及与使用状态判断信息所使用的所有块对应的FAT信息标识符，而保持彼此对应; 以及控制器控制单元，通过使用转换表，FAT信息和块管理表来管理存储在闪速存储器中的数据。

42. 发明授权

US08495651B2 Method and system for performing real-time operation including plural chained tasks using plural processors 失效
标题翻译：用于使用多个处理器执行包括多个链接任务的实时操作的方法和系统
公开(公告)号：US08495651B2
公开(公告)日：2013-07-23
申请号：US10895040
申请日：2004-07-21
申请人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
IPC分类号： G06F9/46
CPC分类号： G06F9/45537 , G06F9/4887 , G06F9/5066
摘要： An information processing system periodically performs a real-time operation including a plurality of chained tasks. The system includes a plurality of processors, a unit for dividing the chained tasks into a first task group and a second task group based on a relationship in order of execution among the tasks, the second task group being executed after the first task group, and a unit for performing a scheduling operation of periodically assigning each of the first task group and the second task group to at least one of the processors to periodically execute the first task group at regular time intervals and periodically execute the second task group at the regular time intervals with a one-period delay relative to the first task group.
摘要翻译：信息处理系统周期性地执行包括多个链接任务的实时操作。该系统包括多个处理器，用于基于在任务之间的执行顺序的关系将链接任务划分为第一任务组和第二任务组的单元，在第一任务组之后执行的第二任务组，以及用于执行将所述第一任务组和所述第二任务组中的每一个周期性地分配给所述处理器中的至少一个的调度操作的单元，以定期的时间间隔周期性地执行所述第一任务组，并且以规则时间周期性地执行所述第二任务组间隔相对于第一个任务组具有一个周期的延迟。

43. 发明授权

US08171477B2 Method and system for performing real-time operation 有权
标题翻译：执行实时操作的方法和系统
公开(公告)号：US08171477B2
公开(公告)日：2012-05-01
申请号：US12172285
申请日：2008-07-14
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/5066
摘要： An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
摘要翻译：信息处理系统执行包括多个任务的组合的实时操作。该系统包括多个处理器，存储结构描述信息的单元和描述与任务相对应的过程的多个程序，表示程序之间的输入/输出中的关系的结构性描述信息，并且包括关于执行所需时间的成本信息每个程序，基于结构描述信息确定用于执行程序的多个线程中的每一个的执行开始时间和执行项的单元，以及执行将线程分配至少的调度操作的单元根据确定的结果，处理器中的一个。

44. 发明授权

US08060925B2 Processor, memory, computer system, and method of authentication 有权
标题翻译：处理器，内存，计算机系统和验证方法
公开(公告)号：US08060925B2
公开(公告)日：2011-11-15
申请号：US11508935
申请日：2006-08-24
申请人： Kenichiro Yoshii , Tatsunori Kanai
发明人： Kenichiro Yoshii , Tatsunori Kanai
IPC分类号： G06F15/16
CPC分类号： G06F12/1466 , G06F21/445 , G06F21/57 , G06F2221/2129
摘要： A processor communicating with a first memory configured to store first information and first data, and communicating with a second memory configured to store second information and second data, includes a computing unit configured to perform computation using the first data and the second data; an storing unit configured integrally with the computing unit to store first authentication information and second authentication information; a reading unit configured to read out the first information and the second information; an authenticating unit configured to authenticate the first memory by comparing the first information and the first authentication information, and to authenticate the second memory by comparing the second information and the second authentication information; and an controlling unit configured to control an access of the computing unit to the first memory and the second memory based on a result of the authentications.
摘要翻译：与被配置为存储第一信息和第一数据的第一存储器通信并与被配置为存储第二信息和第二数据的第二存储器通信的处理器包括被配置为使用第一数据和第二数据执行计算的计算单元; 存储单元，与所述计算单元一体地配置以存储第一认证信息和第二认证信息; 读取单元，被配置为读出第一信息和第二信息; 认证单元，被配置为通过比较第一信息和第一认证信息来认证第一存储器，并且通过比较第二信息和第二认证信息来认证第二存储器; 以及控制单元，被配置为基于所述认证的结果来控制所述计算单元对所述第一存储器和所述第二存储器的访问。

45. 发明授权

US07971014B2 Information processing apparatus and data recovering method 失效
标题翻译：信息处理装置和数据恢复方法
公开(公告)号：US07971014B2
公开(公告)日：2011-06-28
申请号：US12198473
申请日：2008-08-26
申请人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
发明人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
IPC分类号： G06F12/16 , G06F13/00
CPC分类号： G06F11/1441 , G06F11/141
摘要： In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
摘要翻译：在信息处理装置中，当发出写入非易失性的主存储单元的存储内容的指令时，从备份中提取包含在具有读取许可的设置的备份数据中的数据和写入目的地地址存储在非易失性的备份存储单元中的数据。此外，根据从备份数据提取的数据和写入目的地地址，将数据写入由写入目的地址指示的主存储单元的存储区域。

46. 发明授权

US07761779B2 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US07761779B2
公开(公告)日：2010-07-20
申请号：US11519797
申请日：2006-09-13
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： G06F12/14
CPC分类号： G06F11/1032
摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
摘要翻译：访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

47. 发明授权

US07653861B2 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US07653861B2
公开(公告)日：2010-01-26
申请号：US11523003
申请日：2006-09-19
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： H03M13/00
CPC分类号： G06F12/1466 , G06F11/1016 , G06F12/1408 , G06F21/79
摘要： An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.
摘要翻译：一种访问控制装置，包括：写入器校验发生器，其生成写入器掩码数据的写入器校验器以掩蔽奇偶校验相加数据;写入器校验器与写入器访问ID相关联，当写入器请求写入数据到存储器中时访问内存写入掩码生成器，其基于写入器综合符，写入器访问ID和写入器写入写入数据的存储器中的写入地址生成写入器掩模数据; 第一XOR计算器，通过计算奇偶校验相加数据和写入器掩码数据之间的异或来获得第一后操作数据; 以及将写入地址转换成由写入器访问ID确定的另一地址的写入地址转换器。

48. 发明授权

US07356666B2 Local memory management system with plural processors 有权
标题翻译：具有多个处理器的本地存储器管理系统
公开(公告)号：US07356666B2
公开(公告)日：2008-04-08
申请号：US10808320
申请日：2004-03-25
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F9/544 , G06F9/5016
摘要： An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
摘要翻译：信息处理系统包括具有第一本地存储器的第一处理器，具有第二本地存储器的第二处理器和具有第三本地存储器的第三处理器。该系统还包括一个单元，其将第一和第三本地存储器之一映射到要由第一处理器执行的第一线程的有效地址空间的一部分。第二和第三本地存储器中映射的一个是第二和第三处理器中对应的一个处理器的本地存储器，其执行与第一线程交互的第二线程。该系统还包括将本地存储器改变为将第一线程的有效地址空间的一部分映射到第二和第三本地存储器之一的单元。

49. 发明申请

US20070136647A1 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US20070136647A1
公开(公告)日：2007-06-14
申请号：US11519797
申请日：2006-09-13
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： H03M13/00
CPC分类号： G06F11/1032
摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
摘要翻译：访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

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