专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06740583B2 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry 有权
标题翻译：形成集成电路的半导体处理方法和形成动态随机存取存储器（DRAM）电路的半导体处理方法
公开(公告)号：US06740583B2
公开(公告)日：2004-05-25
申请号：US10243156
申请日：2002-09-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L214763
CPC分类号： H01L27/10873 , H01L21/266 , H01L21/31116 , H01L21/31144 , H01L27/10894 , H01L29/6653
摘要： Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
摘要翻译：描述了形成集成电路，特别是动态随机存取存储器（DRAM）电路的半导体处理方法。在一个实施例中，使用单个掩蔽步骤在衬底上形成掩模开口，并且提供两种杂质，并且通过开口蚀刻衬底的材料。在一个实施方案中，在要设置杂质的衬底区域上的光掩模层中以及要进行蚀刻的其它区域同时形成开口。在单独的步骤中，衬底掺杂有杂质，并且通过掩模开口蚀刻衬底的材料。在另一实施方式中，在衬底上形成两条导线，并且在导电线上形成掩模层。在相同步骤中的掩模层中形成开口，其中一个开口被接纳在一个导电线上，另一个开口被接收在另一个导线上。杂质通过靠近一根导电线路的衬底提供到衬底中，并且来自另一导电线的材料通过另一个开口去除，以至少部分地在另一个导电线上形成接触开口。

42. 发明授权

US06583460B1 Method of forming a metal to polysilicon contact in oxygen environment 有权
公开(公告)号：US06583460B1
公开(公告)日：2003-06-24
申请号：US09650071
申请日：2000-08-29
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2972
CPC分类号： H01L21/7687 , H01L21/76802 , H01L21/76831 , H01L21/76877
摘要： A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

43. 发明授权

US06395623B1 Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions 失效
标题翻译：形成与导电线的接触开口的半导体加工方法以及形成衬底有源区源/漏区的方法
公开(公告)号：US06395623B1
公开(公告)日：2002-05-28
申请号：US09141777
申请日：1998-08-27
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21425
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L21/823814 , H01L21/823871
摘要： In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active area to accommodate source/drain doping. In another preferred implementation, desired PMOS regions over a substrate into which p-type impurity is to be provided are exposed while a contact opening is contemporaneously formed to at least one conductive line extending over substrate isolation oxide. In another preferred implementation, a contact opening to a conductive line over a substrate and an opening to a laterally spaced substrate active area are formed in a common masking step. In another preferred implementation, desired PMOS active areas over a substrate are exposed and p-type impurity to a first concentration is provided into desired exposed areas. A masking layer is formed over the substrate and subsequently patterned and etched to form openings over source/drain regions. P-type impurity is provided through the openings into the source/drain regions to a second concentration which is greater than the first concentration.
摘要翻译：一方面，本发明提供一种形成到导线的接触开口的方法。在一个优选实施方案中，接触开口形成为导电线，其覆盖衬底隔离区域，其中蚀刻也向外暴露衬底有源区以适应源极/漏极掺杂。在另一个优选的实施方案中，将要提供p型杂质的衬底上的期望的PMOS区域暴露，同时将接触开口同时形成在至少一个延伸到衬底隔离氧化物上的导电线上。在另一个优选的实施方式中，在通常的掩蔽步骤中形成了在衬底上方的导电线的接触开口和横向间隔开的衬底有源区的开口。在另一个优选的实施方案中，暴露衬底上期望的PMOS有源区，并将第一浓度的p型杂质提供到期望的暴露区域中。掩模层形成在衬底上并随后被图案化和蚀刻以在源/漏区上形成开口。通过开口将P型杂质提供到源极/漏极区域中，达到大于第一浓度的第二浓度。

44. 发明授权

US06395613B1 Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts 有权
公开(公告)号：US06395613B1
公开(公告)日：2002-05-28
申请号：US09651816
申请日：2000-08-30
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L21/76802 , H01L21/76831 , H01L21/76832 , H01L21/76838 , H01L27/0207 , H01L27/10808 , H01L27/1085 , H01L27/10852 , H01L27/10888 , H01L28/40
摘要： Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, capacitors are formed which, according to a one embodiment, form part of a dynamic random access memory (DRAM) array.

45. 发明授权

US06223331B1 Semiconductor circuit design method for employing spacing constraints and circuits thereof 失效
标题翻译：采用间距约束的半导体电路设计方法及其电路
公开(公告)号：US06223331B1
公开(公告)日：2001-04-24
申请号：US09126877
申请日：1998-07-30
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： G06F1750
CPC分类号： H01L27/0207 , H01L27/105
摘要： Semiconductor circuit design methods, semiconductor processing methods, and related integrated circuitry are described. In one embodiment, a spacing constraint is defined and describes a desired spacing between a transistor gate line and a next adjacent structure. A circuit layout is defined to include a plurality of transistor gate lines. From the circuit layout, at least one area is determined wherein the spacing constraint is not met. The circuit layout is modified by defining in the one determined area, at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where the spacing constraint is not met. In another embodiment, a plurality of gate lines are defined which are to be formed over substrate active areas. A determination is made whether a gate line spacing constraint is met wherein the gate line spacing constraint describes a desired spacing between a transistor gate line and a next adjacent transistor gate line. If the spacing constraint is not met, then a space-compensating transistor gate line is added and positioned to satisfy the spacing constraint.
摘要翻译：描述了半导体电路设计方法，半导体处理方法和相关的集成电路。在一个实施例中，限定了间隔约束，并且描述了晶体管栅极线与下一个相邻结构之间的期望间隔。电路布局被定义为包括多个晶体管栅极线。根据电路布局，确定不满足间隔约束的至少一个区域。通过在一个确定的区域中定义电路布局，至少一个附加的空间补偿结构与栅极线横向间隔开，并且下一个相邻结构不满足间隔约束。在另一个实施例中，限定要在衬底有源区上形成的多条栅极线。确定是否满足栅极线间隔约束，其中栅极线间隔约束描述了晶体管栅极线和下一个相邻晶体管栅极线之间的期望间隔。如果不满足间隔约束，则添加并定位空间补偿晶体管栅极线以满足间隔约束。

46. 发明授权

US5909630A Dual-masked isolation 失效
标题翻译：双屏蔽隔离
公开(公告)号：US5909630A
公开(公告)日：1999-06-01
申请号：US86377
申请日：1998-05-28
申请人： Ceredig Roberts , Werner Juengling
发明人： Ceredig Roberts , Werner Juengling
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/32 , H01L21/76221
摘要： A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.
摘要翻译：场隔离过程利用两个或更多个隔离形成步骤在半导体衬底上形成有源区。每个场隔离步骤以减少场氧化物侵蚀的方式形成场隔离的一部分，特别是通过形成场氧化物岛。现场隔离配置的叠加定义了所需的有效区域。目前优选的双掩模方法可以使用单个掩蔽叠层进行，或者更优选地使用用于每个隔离掩模的掩蔽堆叠。本隔离过程进一步允许针对同一集成电路上的各种隔离要求进行优化的隔离特性。

47. 发明授权

US5670412A Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate 失效
标题翻译：在半导体衬底上形成场氧化区的半导体加工方法
公开(公告)号：US5670412A
公开(公告)日：1997-09-23
申请号：US506172
申请日：1995-07-25
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32 , Y10S438/911
摘要： A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Ge.sub.x Si.sub.y layer over the pad oxide layer, where x is greater than 0.2, y is from 0 to 0.8, and x+y=1.0; c) providing a patterned nitride oxidation masking layer over the Ge.sub.x Si.sub.y layer to define at least one pair of adjacent nitride masking blocks overlying desired active area regions of the substrate; d) etching exposed portions of the Ge.sub.x Si.sub.y layer and thereby defining exposed sidewall edges of the Ge.sub.x Si.sub.y layer; e) providing an oxidation restriction layer over the respective Ge.sub.x Si.sub.y sidewalls, the oxidation restriction layer restricting rate of oxidation of the Ge.sub.x Si.sub.y layer from what would otherwise occur if the oxidation restriction layer were not present; f) oxidizing portions of the substrate unmasked by the masking layer to form at least one pair of adjacent SiO.sub.2 substrate field oxide regions; g) stripping the patterned masking layer from the substrate; h) after stripping the masking layer, stripping the Ge.sub.x Si.sub.y layer or any oxidation product therefrom from the substrate selectively relative to SiO.sub.2 ; and i) after stripping the Ge.sub.x Si.sub.y layer or any oxidation product, stripping the pad oxide and any other oxide from the substrate between the pair of adjacent field oxide regions to outwardly expose substrate active area between the pair of field oxide regions. The invention also contemplates products produced by such method.
摘要翻译：形成场氧化物区域的半导体处理方法包括：a）在半导体衬底上提供牺牲衬垫氧化物层; b）在衬垫氧化物层上提供GexSiy层，其中x大于0.2，y为0至0.8，x + y = 1.0; c）在所述GexSiSi层上提供图案化的氮化物氧化掩蔽层以限定覆盖所述衬底的期望有源区域区域的至少一对相邻氮化物掩模块; d）蚀刻GexSiy层的暴露部分，从而限定GexSiy层的暴露的侧壁边缘; e）在相应的GexSiy侧壁上提供氧化限制层，所述氧化限制层限制GexSiy层与不存在氧化限制层时会发生的氧化的速率; f）氧化由掩模层未掩蔽的衬底的部分以形成至少一对相邻的SiO 2衬底场氧化物区域; g）从衬底剥离图案化掩模层; h）在剥离掩蔽层之后，相对于SiO 2选择性地从衬底上剥离GexSiy层或其任何氧化产物; 以及i）在剥离GexSiy层或任何氧化产物之后，在该对相邻的场氧化物区域之间剥离衬垫氧化物和任何其它氧化物，以向外暴露一对场氧化物区域之间的衬底有源区。本发明还考虑了通过这种方法生产的产品。

48. 发明授权

US08557656B2 Cross-hair cell based floating body device 有权
标题翻译：基于跨毛细胞的浮体装置
公开(公告)号：US08557656B2
公开(公告)日：2013-10-15
申请号：US13584590
申请日：2012-08-13
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/8242
CPC分类号： H01L29/7841 , H01L27/10802 , H01L27/10826 , H01L29/785
摘要： A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
摘要翻译：公开了一种具有浮体结构的非平面晶体管及其制造方法。在某些实施例中，晶体管包括具有上和下掺杂区的鳍。上掺杂区域可以形成由在鳍片中形成的浅沟槽分离的源极和漏极。在翅片形成期间，可以在浅沟槽下方形成中空区域，隔离源极和漏极。可以在中空区域中形成氧化物以形成浮体结构，其中源极和漏极彼此隔离，并且形成在鳍下方的衬底。在一些实施例中，独立的偏置门可以邻近翅片的壁形成。在其他实施例中，电耦合栅极可以形成为邻近翅片的壁。

49. 发明授权

US08497550B2 Multi-level DRAM cell using CHC technology 有权
标题翻译：使用CHC技术的多级DRAM单元
公开(公告)号：US08497550B2
公开(公告)日：2013-07-30
申请号：US13046798
申请日：2011-03-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76
CPC分类号： G11C11/4097 , G11C11/565 , H01L27/108 , H01L27/10826 , H01L29/785
摘要： A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
摘要翻译： DRAM存储单元包括：第一finFET结构; 以及与第一finFET结构相邻的第二finFET结构。第二finFET结构包括：第二鳍状结构的第一鳍中的源极跟随器晶体管; 第二鳍式FET结构的第二鳍中的存取晶体管; 写字线以及堆叠在写字线之上的读字线。当读取的字线被激发为高电平时，源极跟随器晶体管使得能够从第一finFET结构读取数据。

50. 发明授权

US08450785B2 Systems and devices including multi-gate transistors and methods of using, making, and operating the same 有权
标题翻译：包括多栅极晶体管的系统和器件及其使用，制造和操作的方法
公开(公告)号：US08450785B2
公开(公告)日：2013-05-28
申请号：US13183337
申请日：2011-07-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L27/088 , H01L29/78
CPC分类号： H01L27/108 , H01L21/845 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L28/91 , H01L29/66795 , H01L29/7851
摘要： Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array.
摘要翻译：公开了形成晶体管的方法。在一个实施例中，通过在衬底中形成多个椭圆形基底并形成椭圆形基底形成翅片来形成晶体管。晶体管形成在鳍内，使得它们可以用作存储器阵列中的存取装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式