专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06882574B2 Single poly UV-erasable programmable read only memory 有权
标题翻译：单个聚UV可擦除可编程只读存储器
公开(公告)号：US06882574B2
公开(公告)日：2005-04-19
申请号：US10605235
申请日：2003-09-17
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/0433 , G11C2216/10 , G11C2216/18 , H01L27/11521 , H01L27/11558
摘要： An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the first P-type MOS transistor connected to source line voltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the second P-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.
摘要翻译：可擦除可编程只读存储器包括两个串联的P型金属氧化物半导体（MOS）晶体管，其中第一P型MOS晶体管用作选择晶体管，第一P型MOS晶体管的栅极耦合到选择栅极电压，连接到源极线电压的第一P型MOS晶体管的第一节点，与第二P型MOS晶体管的第一节点连接的第一P型MOS晶体管的第二节点，其中，第二P型MOS晶体管连接到位线电压，其中第二P型MOS晶体管的栅极用作浮置栅极，其中可擦除可编程只读存储器不需要在控制栅极上偏置一定电压，编程，从而将热载体注入到浮动栅极上，并且其中可擦除可编程只读存储器被对紫外线（UV）光透明的电介质材料封盖。

42. 发明授权

US06750504B2 Low voltage single-poly flash memory cell and array 失效
标题翻译：低电压单聚光闪存单元和阵列
公开(公告)号：US06750504B2
公开(公告)日：2004-06-15
申请号：US10063444
申请日：2002-04-24
申请人： Ching-Sung Yang , Shih-Jye Shen , Wei-Zhe Wong , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Wei-Zhe Wong , Ching-Hsiang Hsu
IPC分类号： H01L2972
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115
摘要： A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.
摘要翻译：低电压单聚光闪存单元包括第一导电类型的第一离子阱，形成在第一离子阱上的第二导电类型的第二离子阱，电荷存储层，其包含第一绝缘层，俘获层，以及位于所述第二离子阱上的第二绝缘层，位于所述电荷存储层上的栅极，位于所述电荷存储层的两侧的所述第二导电类型的源极和漏极以及所述第一导电性的离子掺杂区域形成在所述第二离子阱中并且在所述源的下面和周围以及所述第一绝缘层的底部的至少一部分。

43. 发明授权

US06534817B2 Contactless channel write/erase flash memory cell and its fabrication method 失效
公开(公告)号：US06534817B2
公开(公告)日：2003-03-18
申请号：US09683581
申请日：2002-01-22
申请人： Ching-Hsiang Hsu , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Ching-Sung Yang
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L27/115 , H01L29/7883
摘要： A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N+-doped region that acts as a drain of the flash memory cell and a P-doped region underneath an oxide layer. The N+-doped region and the P-doped region extend to in a bit line direction and a metal contact is used to connect the two away from any of the N+-doped region and the P-doped region of the flash memory cell for decreasing the numbers of the metal contacts in the flash memory cell and reducing dimensions of the device.

44. 发明授权

US06504763B1 Nonvolatile semiconductor memory capable of random programming 失效
标题翻译：非易失性半导体存储器，能够进行随机编程
公开(公告)号：US06504763B1
公开(公告)日：2003-01-07
申请号：US09683845
申请日：2002-02-21
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the first conductivity type isolated by an STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate used to provide a first predetermined voltage for the shallow ion well during a data program mode via a conductive plug which electrically connects to the bit line and extends downward to the shallow ion well. Consequently, during a programming operation, only a selected word line is required to have an appropriate voltage applied to it. Thus, the power needed is reduced and access time is shortened.
摘要翻译：能够进行随机编程的非易失性半导体存储器具有具有存储区域的第一导电类型的半导体衬底，位于存储区域内的半导体衬底中的第二导电类型的深离子阱，第一导电类型的浅离子阱通过深离子阱内的STI层隔离，位于浅离子阱内的半导体衬底上的至少一个NAND单元块，以及位于半导体衬底上方的位线，用于为浅离子阱提供第一预定电压通过电连接到位线并向下延伸到浅离子阱的导电插头的数据程序模式。因此，在编程操作期间，仅需要选择的字线来施加适当的电压。因此，所需的功率减少，并且访问时间缩短。

45. 发明授权

US06490196B1 Method for operating a nonvolatile memory having embedded word lines 失效
标题翻译：用于操作具有嵌入字线的非易失性存储器的方法
公开(公告)号：US06490196B1
公开(公告)日：2002-12-03
申请号：US10064047
申请日：2002-06-04
申请人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
IPC分类号： G11C1604
CPC分类号： H01L29/42336 , G11C8/14 , G11C11/5671 , G11C16/0475 , G11C16/08 , H01L27/115 , H01L29/7883
摘要： A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
摘要翻译：提供具有能够存储两位信息的嵌入式门结构和这种闪存单元的操作的闪存单元。作为源极端子的第一离子掺杂区域形成在半导体衬底中。嵌入栅极结构和第二离子掺杂区域交替地布置在第一离子掺杂区域上。嵌入式栅极结构被第一氧化物层，俘获层和第二氧化物层包围。在嵌入式栅极结构上形成绝缘层。扩散漏极位于第二离子掺杂区域顶部，导电层与扩散漏极连接。嵌入式栅极结构与绝缘层与扩散漏极隔离。此外，提供了具有两位信息的存储单元的读取，编程和擦除操作。

46. 发明申请

US20120276700A1 READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：只读存储器及其制造方法
公开(公告)号：US20120276700A1
公开(公告)日：2012-11-01
申请号：US13549525
申请日：2012-07-16
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
IPC分类号： H01L21/336
CPC分类号： H01L27/112 , G11C17/12 , H01L27/1126
摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
摘要翻译：掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。第二ROM位包括第二MOS晶体管。

47. 发明申请

US20090134452A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20090134452A1
公开(公告)日：2009-05-28
申请号：US12341984
申请日：2008-12-22
申请人： Ching-Sung Yang , Wei-Zhe Wong
发明人： Ching-Sung Yang , Wei-Zhe Wong
IPC分类号： H01L29/792
CPC分类号： H01L29/7887 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row.
摘要翻译：非易失性存储器包括衬底，存储器单元阵列，（N + 1）位线，M字线，M个第一控制栅极线和M个第二控制栅极线。存储单元阵列包括N个存储单元列，每个存储单元列包括M个存储单元。（N + 1）位线设置在基板上，并且在列方向上并列布置，并且（N + 1）位线对应于N个存储单元列。 M字线设置在基板上并且在行方向上平行布置。 M个第一控制栅极线在行方向上平行布置在基板上，并且分别连接到同一行中的第一存储单元。 M个第二控制栅极线在行方向上平行布置在基板上，并分别连接到同一行中的第二存储单元。

48. 发明授权

US07491607B2 Method of fabricating flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US07491607B2
公开(公告)日：2009-02-17
申请号：US11750320
申请日：2007-05-17
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/3468 , H01L21/28273 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.
摘要翻译：提供闪存单元。将深井设置在基板中，并将井设置在深井内。层叠栅极结构设置在基板上。源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。选择栅极设置在堆叠的栅极结构和源极区域之间。第一栅极介电层设置在选择栅极和堆叠栅极结构之间。第二栅极电介质层设置在选择栅极和衬底之间。在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。衬底上的导电插塞延伸穿过漏区和深掺杂区。

49. 发明申请

US20080316791A1 OPERATING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY 有权
标题翻译：一次性编程只读存储器的操作方法
公开(公告)号：US20080316791A1
公开(公告)日：2008-12-25
申请号：US12191844
申请日：2008-08-14
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： H01L27/112 , H01L27/11206
摘要： The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.
摘要翻译：本发明提供一种操作一次性可编程只读存储器（OTPROM）的方法。 OTPROM至少包括设置在基板上的选择晶体管，电极和电介质层，其中电极设置在选择晶体管的源极区域上，电介质层被设置在电极和源极区域之间。操作一次性可编程只读存储器的方法包括执行编程操作以将数字数据值“1”写入存储器，并执行编程操作以将数字数据值“0”写入存储器。

50. 发明授权

US07336539B2 Method of operating flash memory cell 有权
标题翻译：操作闪存单元的方法
公开(公告)号：US07336539B2
公开(公告)日：2008-02-26
申请号：US11750323
申请日：2007-05-17
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： G11C16/02 , G11C16/12 , G11C16/14 , G11C16/26
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/3468 , H01L21/28273 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.
摘要翻译：提供闪存单元。将深井设置在基板中，并将井设置在深井内。层叠栅极结构设置在基板上。源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。选择栅极设置在堆叠的栅极结构和源极区域之间。第一栅极介电层设置在选择栅极和堆叠栅极结构之间。第二栅极电介质层设置在选择栅极和衬底之间。在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。衬底上的导电插塞延伸穿过漏区和深掺杂区。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式