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41. 发明申请

US20080211020A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080211020A1
公开(公告)日：2008-09-04
申请号：US12019228
申请日：2008-01-24
申请人： Wataru SAITO
发明人： Wataru SAITO
IPC分类号： H01L29/78
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/7811
摘要： A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a lateral direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer; and a sixth first-conductivity-type semiconductor layer provided on the major surface of the first first-conductivity-type semiconductor layer in a termination section outside the periodic array structure. The second first-conductivity-type semiconductor layer has an impurity concentration varying in the lateral direction and the impurity concentration is minimized at a center in the lateral direction. An impurity concentration in the sixth first-conductivity-type semiconductor layer is not higher than the impurity concentration at the center of the second first-conductivity-type semiconductor layer.
摘要翻译：一种半导体装置，包括：第一第一导电型半导体层; 设置在所述第一第一导电型半导体层的主表面上的第二第一导电型半导体层; 第三第二导电型半导体层，其在与所述第一第一导电型半导体层的主表面大致平行的横向方向上与所述第二第一导电型半导体层组合形成周期性阵列结构; 以及设置在周期性阵列结构外部的终端部分中的第一第一导电型半导体层的主表面上的第六第一导电型半导体层。第二第一导电型半导体层的横向的杂质浓度变化，并且在横向的中心处的杂质浓度最小化。第六第一导电型半导体层中的杂质浓度不高于第二第一导电型半导体层的中心处的杂质浓度。

42. 发明申请

US20070228462A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20070228462A1
公开(公告)日：2007-10-04
申请号：US11693157
申请日：2007-03-29
申请人： Wataru SAITO
发明人： Wataru SAITO
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/4238 , H01L29/7811
摘要： A power semiconductor device includes: a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on a first semiconductor layer and alternately arranged along at least one direction parallel to an upper face of the first semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively formed in an upper face of the second and third semiconductor layers; and a control electrode formed above the second, third and fourth semiconductor layers via a gate insulating film. The control electrode includes: first portions periodically arranged along a first direction selected from arranging directions of the third semiconductor layer, the third semiconductor layer has a shortest arrangement period in the first direction, and second portions periodically arranged along a second direction, the second direction being parallel to the upper face of the first semiconductor layer and crossing the first direction. The arrangement period of the first portions is m times the arrangement period of the third semiconductor layer, where m is an integer not less than 2.
摘要翻译：功率半导体器件包括：第一导电类型的第二半导体层和形成在第一半导体层上并沿着平行于第一半导体层的上表面的至少一个方向交替布置的第二导电类型的第三半导体层; 选择性地形成在第二和第三半导体层的上表面中的第二导电类型的第四半导体层; 以及通过栅极绝缘膜形成在第二，第三和第四半导体层上方的控制电极。控制电极包括：沿着从第三半导体层的布置方向选择的第一方向周期性地布置的第一部分，第三半导体层在第一方向上具有最短的布置周期，并且沿第二方向周期性地布置第二部分，第二方向平行于第一半导体层的上表面并与第一方向交叉。第一部分的布置周期是第三半导体层的布置周期的m倍，其中m是不小于2的整数。

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