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41. 发明授权

US07560318B2 Process for forming an electronic device including semiconductor layers having different stresses 有权
标题翻译：用于形成包括具有不同应力的半导体层的电子器件的工艺
公开(公告)号：US07560318B2
公开(公告)日：2009-07-14
申请号：US11374372
申请日：2006-03-13
申请人： Mariam G. Sadaka , Venkat R. Kolagunta , William J. Taylor , Victor H. Vartanian
发明人： Mariam G. Sadaka , Venkat R. Kolagunta , William J. Taylor , Victor H. Vartanian
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/76256 , H01L27/1203 , H01L29/7842 , H01L29/785 , H01L29/78687
摘要： An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
摘要翻译：电子设备可以具有位于第一半导体层和基底层之间的绝缘层。与第一半导体层相比具有不同组成和应力的第二半导体层可以覆盖在第一半导体层的至少一部分上。在一个实施例中，第一电子部件可以包括第一有源区，其包括第一和第二半导体层的第一部分。第二电子部件可以包括可以包括第一半导体层的第二部分的第二有源区。可以使用不同的过程来形成电子设备。在另一个实施例中，可以执行退火工件，并且可以改变至少一个半导体层的应力。在不同的实施例中，退火工件可以在第二半导体层的形成之前或之后进行。

42. 发明申请

US20090035914A1 ISOLATION TRENCH PROCESSING FOR STRAIN CONTROL 有权
标题翻译：用于应变控制的隔离加速处理
公开(公告)号：US20090035914A1
公开(公告)日：2009-02-05
申请号：US11831400
申请日：2007-07-31
申请人： Mariam G. Sadaka , Michael A. Mendicino
发明人： Mariam G. Sadaka , Michael A. Mendicino
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L29/78 , H01L29/7846
摘要： A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region.
摘要翻译：半导体制造工艺包括在绝缘体上硅（SOI）晶片的有源层上形成例如氮化硅的硬掩模，去除硬掩模和有源层的一部分以形成沟槽，以及形成隔离电介质在沟槽中，电介质在有源层的沟道区上施加压应变。形成电介质可以包括进行热氧化。在进行热氧化之前，半导体结构可以例如通过外延形成在沟槽的侧壁上。该结构可以是硅或硅化合物，例如硅锗。在热氧化期间，半导体结构被消耗。在硅锗的情况下，锗可以在热氧化期间扩散以产生硅锗通道区。

43. 发明授权

US07435639B2 Dual surface SOI by lateral epitaxial overgrowth 有权
标题翻译：通过横向外延过度生长的双面SOI
公开(公告)号：US07435639B2
公开(公告)日：2008-10-14
申请号：US11443627
申请日：2006-05-31
申请人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
发明人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.
摘要翻译：半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件获得。

44. 发明授权

US07163903B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07163903B2
公开(公告)日：2007-01-16
申请号：US10836172
申请日：2004-04-30
申请人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
发明人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

45. 发明授权

US06803248B2 Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers 有权
标题翻译：在InGaAsP上蚀刻四面体界面层的化学，主要形成在GaAs和In x Ga（1-x）P层之间
公开(公告)号：US06803248B2
公开(公告)日：2004-10-12
申请号：US10029093
申请日：2001-12-21
申请人： Mariam G. Sadaka , Jonathan K. Abrokwah
发明人： Mariam G. Sadaka , Jonathan K. Abrokwah
IPC分类号： H01L2100
CPC分类号： H01L29/66318 , H01L21/30612
摘要： A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.
摘要翻译：提供了一种用于蚀刻异质结双极晶体管（HBT）中的GaAs和InGaP层之间的In x Ga 1-x As y P 1-y的四面体界面层的方法。根据该方法，通过用对InGaP有选择性的蚀刻剂蚀刻GaAs层来暴露界面。然后用对InGaP有选择性的稀HCl水溶液和H 2 O 2蚀刻该界面。通过该方法提供的受控蚀刻使得HBT可以制造成具有更复杂的近似理想设计，其可以包含多个GaAs / InGaP界面。

46. 发明授权

US06465297B1 Method of manufacturing a semiconductor component having a capacitor 有权
标题翻译：制造半导体部件及其半导体部件的方法
公开(公告)号：US06465297B1
公开(公告)日：2002-10-15
申请号：US09679861
申请日：2000-10-05
申请人： Haldane S. Henry , Darrell G. Hill , Jonathan K. Abrokwah , Mariam G. Sadaka
发明人： Haldane S. Henry , Darrell G. Hill , Jonathan K. Abrokwah , Mariam G. Sadaka
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/31616 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor component includes forming a first capacitor electrode (126) over a substrate (110), forming a capacitor dielectric layer (226) over the first capacitor electrode, and forming a second capacitor electrode (326) over the capacitor dielectric layer. The capacitor dielectric layer is made of aluminum.
摘要翻译：一种制造半导体部件的方法包括在基板（110）上形成第一电容电极（126），在所述第一电容器电极上形成电容器电介质层（226），在所述电容器电介质上形成第二电容电极（326）层。电容器介质层由铝制成。

47. 发明授权

US06368929B1 Method of manufacturing a semiconductor component and semiconductor component thereof 有权
标题翻译：制造半导体部件及其半导体部件的方法
公开(公告)号：US06368929B1
公开(公告)日：2002-04-09
申请号：US09641002
申请日：2000-08-17
申请人： Darrell G. Hill , Mariam G. Sadaka , Jonathan K. Abrokwah
发明人： Darrell G. Hill , Mariam G. Sadaka , Jonathan K. Abrokwah
IPC分类号： H01L21331
CPC分类号： H01L29/66318
摘要： A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).
摘要翻译：一种制造半导体部件及其部件的方法包括在发射极层（280）中的钝化凸缘（640）的一部分上形成介电层（620），并将基极触点（660）重叠到电介质层（620）上）。

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