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41. 发明授权

US08878295B2 DMOS transistor with a slanted super junction drift structure 有权
标题翻译：具有倾斜超结漂移结构的DMOS晶体管
公开(公告)号：US08878295B2
公开(公告)日：2014-11-04
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

42. 发明申请

US20120091501A1 Low triggering voltage DIAC structure 有权
标题翻译：低触发电压DIAC结构
公开(公告)号：US20120091501A1
公开(公告)日：2012-04-19
申请号：US12925277
申请日：2010-10-18
申请人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
发明人： Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/87 , H01L27/0262 , H01L29/66121
摘要： In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
摘要翻译：在包括连接到高压节点的n +和p +区以及连接到低电压节点的n +和p +区的DIAC类器件中，在连接到低电压节点的n +和p +区之间形成至少两个MOS器件高压节点，连接到低电压节点的n +和p +区域。

43. 发明授权

US07839242B1 Magnetic MEMS switching regulator 有权
标题翻译：磁性MEMS开关调节器
公开(公告)号：US07839242B1
公开(公告)日：2010-11-23
申请号：US11893535
申请日：2007-08-16
申请人： Peter J. Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
发明人： Peter J. Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
IPC分类号： H01H51/34
CPC分类号： H02M3/34
摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
摘要翻译： MEMS磁通开关被制造为铁磁芯。芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。

44. 发明授权

US07800127B1 ESD protection device with controllable triggering characteristics using driver circuit related to power supply 有权
标题翻译：具有可控触发特性的ESD保护器件使用与电源相关的驱动电路
公开(公告)号：US07800127B1
公开(公告)日：2010-09-21
申请号：US11503593
申请日：2006-08-14
申请人： Vladislav Vashchenko , Alexander Burinskiy , Peter J. Hopper , Vladimir Kuznetsov
发明人： Vladislav Vashchenko , Alexander Burinskiy , Peter J. Hopper , Vladimir Kuznetsov
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/87
摘要： In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.
摘要翻译：在用于基于BSCR或NLDMOS-SCR的快速切换应用的ESD装置中，阳极结控制电极通过不将阳极电极连接到BSCR的集电极或NLDMOS-SCR的漏极而提供，并且阴极结通过在BSCR中的附加n +区域或NLDMOS-SCR的p阱中的附加p +区域形成控制电极。通过使用RC定时器驱动器电路控制一个或两个控制电极，在延迟之后调整ESD装置的触发电压。

45. 发明授权

US07795102B1 ESD high frequency diodes 有权
标题翻译： ESD高频二极管
公开(公告)号：US07795102B1
公开(公告)日：2010-09-14
申请号：US11654735
申请日：2007-01-17
申请人： Vladislav Vashchenko , Vladimir Kuznetsov , Peter J. Hopper
发明人： Vladislav Vashchenko , Vladimir Kuznetsov , Peter J. Hopper
IPC分类号： H01L21/331
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/161 , H01L29/66128
摘要： In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.
摘要翻译：在SiGe BJT工艺中，通过限定BJT集电极和BJT内部基极之间的pn结，形成二极管，阻挡BJT的外部栅极区域，并以与内部基底相同的掺杂剂类型掺杂BJT的发射极多晶，使用发射极接触来定义与内部基座的接触。通过子集电极或通过掺杂与收集器相同的掺杂剂类型的第二发射极多晶硅和内部基极建立与集电极的电接触。

46. 发明授权

US07521310B1 Vertical thyristor in complementary SiGe bipolar process 有权
标题翻译：互补SiGe双极工艺中的垂直晶闸管
公开(公告)号：US07521310B1
公开(公告)日：2009-04-21
申请号：US11261235
申请日：2005-10-29
申请人： Vladislav Vashchenko , Alexel Sadovnikov , Peter J. Hopper
发明人： Vladislav Vashchenko , Alexel Sadovnikov , Peter J. Hopper
IPC分类号： H01L21/8238
CPC分类号： H01L27/0817 , H01L21/8222 , H01L27/0641
摘要： In a complementary SiGe bipolar process, a pnpn thyristor structure is formed from some of the layers of a pnp transistor and an npn transistor formed on top of each other and making use of the SiGe gates to define the blocking junction.
摘要翻译：在互补的SiGe双极工艺中，pnpn晶闸管结构由形成在顶部上的pnp晶体管和npn晶体管的一些层形成，并且利用SiGe栅极来限定阻挡结。

47. 发明授权

US07285805B1 Low reference voltage ESD protection device 有权
标题翻译：低参考电压ESD保护器件
公开(公告)号：US07285805B1
公开(公告)日：2007-10-23
申请号：US11503594
申请日：2006-08-14
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L29/86 , H01L21/33 , H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436
摘要： In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.
摘要翻译：在低电压ESD保护器件中，通过不连接LVTSCR的n +漏极和p +发射极区域，并通过连接NMOS的二极管来控制控制电极，产生额外的控制电极。

48. 发明授权

US07259411B1 Vertical MOS transistor 有权
标题翻译：垂直MOS晶体管
公开(公告)号：US07259411B1
公开(公告)日：2007-08-21
申请号：US10728132
申请日：2003-12-04
申请人： Peter J. Hopper , Yuri Mirgorodski , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Yuri Mirgorodski , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823885 , H01L21/823487 , H01L29/0653 , H01L29/0657 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
摘要翻译：垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽。垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

49. 发明授权

US07221036B1 BJT with ESD self protection 有权
标题翻译： BJT具有ESD自保护功能
公开(公告)号：US07221036B1
公开(公告)日：2007-05-22
申请号：US11129957
申请日：2005-05-16
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译：将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。

50. 发明授权

US07119431B1 Apparatus and method for forming heat sinks on silicon on insulator wafers 有权
标题翻译：用于在绝缘体硅片上形成散热片的装置和方法
公开(公告)号：US07119431B1
公开(公告)日：2006-10-10
申请号：US10665897
申请日：2003-09-18
申请人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L23/34 , H01L27/12
CPC分类号： H01L29/78606 , H01L23/3677 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.
摘要翻译：散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。该装置包括形成在晶片的有源硅层中的晶体管。活性表面形成在氧化物层和体硅层上。在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。塞子延伸穿过本体层的厚度到氧化物层。此后，塞子填充有导热材料，例如金属或DAG（导热浆）。在运行期间，来自晶体管的热量通过散热器消散。在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

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