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    • 43. 发明申请
    • Dynamic cross fading method and apparatus
    • 动态交叉衰落方法和装置
    • US20050219418A1
    • 2005-10-06
    • US10818408
    • 2004-04-05
    • Victor ChanRaymond Chow
    • Victor ChanRaymond Chow
    • G06T3/00G09G5/00G09G5/36G09G5/39H04N5/262H04N5/265H04N9/74
    • H04N9/74H04N5/265
    • Provided is a method and apparatus for dynamic cross fading. Specifically, an embedded system can display an image produced from a blend of other images. Initially, a first image and a second image are stored in a buffer in a display controller. Then, the display controller extracts pixels from corresponding locations in the first image and the second image. The pixels are combined with weights associated with each image to perform the cross fade calculation. Consequently, the result from the cross fade calculation is transmitted to a display unit connected to the display controller for viewing. The result can also be fetched during a refresh of a panel in the display unit. In either case, the result is transmitted to a display pipe during dynamic cross fading. Thus, any images stored in the buffer remain unchanged.
    • 提供了一种用于动态交叉衰落的方法和装置。 具体来说,嵌入式系统可以显示从其他图像的混合产生的图像。 最初,将第一图像和第二图像存储在显示控制器中的缓冲器中。 然后,显示控制器从第一图像和第二图像中的相应位置提取像素。 将像素与与每个图像相关联的权重组合以执行交叉淡入淡出计算。 因此,交叉淡入淡出计算的结果被发送到与显示控制器连接的显示单元进行观看。 结果还可以在刷新显示单元中的面板时获取。 在任一情况下,在动态交叉衰落期间将结果传输到显示管道。 因此,存储在缓冲器中的任何图像保持不变。
    • 46. 发明申请
    • SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE
    • 用于最佳CMOS器件性能的基板工程
    • US20050001290A1
    • 2005-01-06
    • US10604003
    • 2003-06-20
    • Victor ChanMeikei LeongMin Yang
    • Victor ChanMeikei LeongMin Yang
    • H01L21/8238H01L29/76
    • H01L21/823807
    • An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
    • 提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件(CMOS)即PFET和NFET的集成半导体结构,其中每个CMOS器件被制造成使得每个器件的电流是最佳的。 具体地,该结构包括具有(110)表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。 所述至少一个PFET具有沿<110>方向的电流,并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。 还提供了诸如集成半导体结构的制造方法。
    • 48. 发明授权
    • Dual trench isolation for CMOS with hybrid orientations
    • 具有混合取向的CMOS的双沟槽隔离
    • US08097516B2
    • 2012-01-17
    • US12169991
    • 2008-07-09
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • Victor ChanMeikei IeongRajesh RengarajanAlexander ReznicekChun-yung SungMin Yang
    • H01L21/336
    • H01L21/76229
    • The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
    • 本发明提供了一种半导体结构,其中不同类型的器件位于混合衬底的特定晶体取向上,这增强了每种器件的性能。 在本发明的半导体结构中,采用双沟槽隔离方案,由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离,而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构,其中pFET位于(110)结晶平面上,而nFET位于(100)晶面上。 根据本发明,不同极性的器件,即nFET和pFETs是大块状器件。