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41. 发明授权

US06159797A Method of fabricating a flash memory with a planarized topography 失效
标题翻译：制造具有平面化地形的闪速存储器的方法
公开(公告)号：US06159797A
公开(公告)日：2000-12-12
申请号：US137668
申请日：1998-08-20
申请人： Tzung-Han Lee
发明人： Tzung-Han Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/66545
摘要： A method of fabricating a flash memory includes successive formation of a first polysilicon layer, a first dielectric layer and a hard material layer on a substrate with a tunnelling oxide layer. Then the hard material layer, the first dielectric layer and the first polysilicon layer are defined and the first polysilicon layer serves as a floating gate of the flash memory. After the step of definition, a source/drain region is formed on the substrate on the sides of the floating gate and an insulating spacer is also formed thereon. An inter-poly dielectric layer is then formed over the substrate and CMP is performed to etch back the inter-poly dielectric layer, exposing the surface of the hard material layer serving as a stop layer. Next, the hard material layer is removed and the first polysilicon layer is doped with impurities. A second dielectric layer is formed over the substrate and covers the surface of the first polysilicon layer. Subsequently, the second polysilicon layer is formed and defined to serve as a control gate of the flash memory.
摘要翻译：制造闪速存储器的方法包括在具有隧道氧化物层的衬底上连续地形成第一多晶硅层，第一介电层和硬质材料层。然后，确定硬质材料层，第一介质层和第一多晶硅层，并且第一多晶硅层用作闪存的浮动栅极。在定义步骤之后，在浮置栅极的侧面上的基板上形成源极/漏极区域，并且还在其上形成绝缘间隔物。然后在衬底上形成多晶硅介电层，并执行CMP以回蚀多晶硅介电层，暴露作为停止层的硬质材料层的表面。接下来，去除硬质材料层，并且第一多晶硅层掺杂有杂质。第二电介质层形成在衬底上并覆盖第一多晶硅层的表面。随后，第二多晶硅层形成并限定为用作闪存的控制栅极。

42. 发明授权

US6146971A Process for forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的工艺
公开(公告)号：US6146971A
公开(公告)日：2000-11-14
申请号：US491574
申请日：2000-01-26
申请人： Chun-Lung Chen , Hsi-Mao Hsiao , Hung-Chen Yu , Tzung-Han Lee
发明人： Chun-Lung Chen , Hsi-Mao Hsiao , Hung-Chen Yu , Tzung-Han Lee
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method is used to form a shallow trench isolation structure. According to the invention, prior to performing CMP on a HDPCVD oxide layer, a smoothing step is performed on the HDPCVD oxide layer to smooth the peak profile of the oxide layer to reduce the moment resulting from the CMP on the peak, and to prevent the later-formed shallow trench isolation structure from being pulled out. In addition, since the invention prevents the later-formed shallow trench isolation structure from being pulled out, the particles resulting from the oxide pulled out from the shallow trench are reduced. Thus, particle damage to the surface of the wafer is reduced.
摘要翻译：使用一种方法来形成浅沟槽隔离结构。根据本发明，在HDPCVD氧化物层上执行CMP之前，对HDPCVD氧化物层进行平滑化步骤以平滑氧化物层的峰面，以减少峰上由CMP产生的力矩，并防止后来形成的浅沟槽隔离结构被拉出。此外，由于本发明防止后来形成的浅沟槽隔离结构被拉出，所以从浅沟槽拉出的氧化物产生的颗粒减小。因此，晶片表面的颗粒损伤减小。

43. 发明授权

US6071769A Method for forming a resistor load of a static random access memory 失效
标题翻译：形成静态随机存取存储器的电阻负载的方法
公开(公告)号：US6071769A
公开(公告)日：2000-06-06
申请号：US998602
申请日：1997-12-29
申请人： Tzung-Han Lee , Han Lin
发明人： Tzung-Han Lee , Han Lin
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/8234
CPC分类号： H01L27/11 , H01L27/1112
摘要： A method for manufacturing SRAM loads comprising the steps of sequentially forming a silicon oxide layer and a silicon nitride layer over a polysilicon layer. Then, the silicon oxide layer and the silicon nitride layer are patterned to form vias exposing a load region. Thereafter, using a thermal oxidation operation, an oxide layer is formed above the load region. Subsequently, the silicon nitride layer and the silicon oxide layer are removed. Through the formation of an oxide layer over the load region, the cross-sectional thickness and width of the load are reduced, thereby moderating the out-diffusion of ions while maintaining the load resistance. Furthermore, the oxide layer, which forms over the load region in the back-end process, can serve as a barrier layer preventing the out-diffusion of ions and blocking incoming moisture.
摘要翻译：一种用于制造SRAM负载的方法，包括以下步骤：在多晶硅层上依次形成氧化硅层和氮化硅层。然后，将氧化硅层和氮化硅层图案化以形成暴露负载区域的通孔。此后，使用热氧化操作，在负载区域的上方形成氧化物层。随后，去除氮化硅层和氧化硅层。通过在负载区域上形成氧化物层，减小了负载的横截面厚度和宽度，从而缓和了离子的扩散，同时保持了负载电阻。此外，在后端工艺中在负载区域上形成的氧化物层可以用作防止离子的扩散和阻止进入的水分的阻挡层。

44. 发明授权

US08779494B2 High-k metal gate random access memory 有权
标题翻译：高k金属门随机存取存储器
公开(公告)号：US08779494B2
公开(公告)日：2014-07-15
申请号：US13426825
申请日：2012-03-22
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L27/10885 , H01L27/10891
摘要： The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.
摘要翻译：本公开涉及高k金属栅极随机存取存储器。存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。衬底具有多个沟槽，并且位线单元布置在衬底上。源极区域设置在位线单元上，栅极结构设置在源极区域上。每个栅极结构具有形成在其中的金属栅极和沟道区域。栅极结构顶部带有漏极区域。字线单元布置在源区和漏区之间。电容单元设置在漏极区域上。还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

45. 发明授权

US08703562B2 Manufacturing method of random access memory 有权
标题翻译：随机存取存储器的制造方法
公开(公告)号：US08703562B2
公开(公告)日：2014-04-22
申请号：US13426832
申请日：2012-03-22
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
IPC分类号： H01L21/8238
CPC分类号： H01L27/10894 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.
摘要翻译：随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。

46. 发明申请

US20130119448A1 MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE 有权
标题翻译：存储器布局结构和存储器结构
公开(公告)号：US20130119448A1
公开(公告)日：2013-05-16
申请号：US13343668
申请日：2012-01-04
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891 , H01L28/90
摘要： A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.
摘要翻译：存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

47. 发明申请

US20130052786A1 FABRICATING METHOD OF DRAM STRUCTURE 有权
标题翻译： DRAM结构的制作方法
公开(公告)号：US20130052786A1
公开(公告)日：2013-02-28
申请号：US13297276
申请日：2011-11-16
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66545
摘要： A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.
摘要翻译： DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。

48. 发明授权

US08288224B2 Method for manufacturing capacitor lower electrodes of semiconductor memory 有权
标题翻译：制造半导体存储器的电容器下电极的方法
公开(公告)号：US08288224B2
公开(公告)日：2012-10-16
申请号：US12699399
申请日：2010-02-03
申请人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
发明人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
IPC分类号： H01L21/8242
CPC分类号： H01L28/92
摘要： A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.
摘要翻译：制造电容器下电极的方法包括电介质层，第一氮化硅层和硬掩模层; 部分地蚀刻硬掩模层，第一氮化硅层和电介质层以形成多个凹部; 在所述硬掩模层上沉积第二氮化硅层并进入所述凹部; 部分蚀刻第二氮化硅层，硬掩模层和电介质层以形成多个沟槽; 在每个沟槽内形成电容器下电极，并部分地蚀刻第一氮化硅层，第二氮化硅层，电介质层和电容器下电极以形成蚀刻区域; 并且从蚀刻区域蚀刻除去电介质层，由此每个电容器下电极的周围被第二氮化硅层包围并附着。

49. 发明授权

US07358556B2 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US07358556B2
公开(公告)日：2008-04-15
申请号：US11416926
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

50. 发明授权

US07357708B2 Anchor structure for fans 失效
标题翻译：球迷的锚结构
公开(公告)号：US07357708B2
公开(公告)日：2008-04-15
申请号：US10665500
申请日：2003-09-22
申请人： Tzung-Han Lee
发明人： Tzung-Han Lee
IPC分类号： H05K5/00
CPC分类号： H05K7/20172 , F04D29/601
摘要： An anchor structure for fans mainly to fasten a fan to an installation object without damaging the fan structure includes coupling members for fastening through holes formed on the corners of the fan. Each of the coupling members includes a first fastening element running through the through hole from the rear end thereof and a second fastening element running though the front end of the through hole to engage with the first fastening element so that the coupling members are fastened securely to maintain the fan structure in an integrated manner to perform normal operation.
摘要翻译：用于主要将风扇固定到安装对象而不损坏风扇结构的风扇的锚结构包括用于通过形成在风扇角部上的孔紧固的联接构件。每个联接构件包括从其后端延伸通过通孔的第一紧固元件和贯穿通孔的前端延伸的第二紧固元件，以与第一紧固元件接合，使得联接构件牢固地紧固到以一体化的方式维护风扇结构，以正常运行。

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