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    • 41. 发明申请
    • SEMICONDUCTOR DEVICE INCLUDING BIT LINE GROUPS
    • 包括位线组的半导体器件
    • US20100135063A1
    • 2010-06-03
    • US12628835
    • 2009-12-01
    • Kiyoshi NakaiShuichi Tsukada
    • Kiyoshi NakaiShuichi Tsukada
    • G11C7/12G11C11/00G11C7/00
    • G11C7/18G11C2207/005
    • A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.
    • 半导体器件包括:第一读/写放大器; 第二读/写放大器; 属于第一读/写放大器的第一组位线; 属于第二读/写放大器的第二组位线,并与第一组位线混合。 第一组位线之一和第二组位线之一并行选择。 将参考电位提供给与从第一组位线选择的第一选定位线相邻的第一非选择位线中的至少一个以及与第二组相邻的第二非选择位线中的至少一个 从第一组位线选择的选定位线。 将第一和第二未选择位线中的剩余的位中的至少一个设置为浮置状态。
    • 43. 发明申请
    • Inspection contact structure and probe card
    • 检查接触结构和探针卡
    • US20080211528A1
    • 2008-09-04
    • US11819273
    • 2007-06-26
    • Takashi AmemiyaShuichi Tsukada
    • Takashi AmemiyaShuichi Tsukada
    • G01R31/02H01R12/00
    • H01R13/2464G01R1/07314G01R1/0735H01R2201/20
    • In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.
    • 在本发明中,在探针卡的电路基板的下表面侧安装有检查接触结构。 在检查接触结构中,具有突出导电部分的弹性片分别安装在硅树脂基底的两个表面上。 硅基板在垂直方向上形成有通过其的通电路径,并且片状导电部分从上方和下方与导流路径接触。 上侧的导电部与电路基板的连接端子接触。 在检查晶片的电性的时候,晶片上的电极焊盘被压在下侧的导电部分上,从而与它们接触。
    • 44. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07362636B2
    • 2008-04-22
    • US11516701
    • 2006-09-07
    • Shuichi Tsukada
    • Shuichi Tsukada
    • G11C7/00
    • G11C11/4091G11C5/146G11C7/065G11C11/4074G11C2207/065
    • A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair; a back bias generating circuit which generates a back bias voltage to be applied to the first NMOS transistors in a state in which a predetermined current is flowing through a second NMOS transistor having approximately the same operating characteristic as that of the first NMOS transistors, and performs a feedback control in response to a threshold voltage of the second NMOS transistor; and control means which performs control in a sensing operation of the sense amplifier such that the pair of first NMOS transistors operates previously and after a lapse of a predetermined time the pair of first PMOS transistors operates.
    • 一种半导体存储器件,包括:读出放大器,包括一对第一NMOS晶体管和连接到位线对作为互补对的一对PMOS晶体管; 背偏置产生电路,其在预定电流流过具有与第一NMOS晶体管的工作特性大致相同的第二NMOS晶体管的状态下产生要施加到第一NMOS晶体管的反向偏置电压,并执行 响应于所述第二NMOS晶体管的阈值电压的反馈控制; 以及控制装置,其在感测放大器的感测操作中执行控制,使得该对第一NMOS晶体管先前工作,并且在该对第一PMOS晶体管工作之后经过预定时间。
    • 45. 发明授权
    • Semiconductor circuit device
    • 半导体电路器件
    • US07224186B2
    • 2007-05-29
    • US11060391
    • 2005-02-17
    • Shuichi Tsukada
    • Shuichi Tsukada
    • H03K19/0175
    • H03K19/018521H03K19/0013H03K19/0027H03K19/01707
    • The present invention relates to a semiconductor circuit device including a logic circuit and a signal line driving circuit. The logic circuit is operated at high supply voltage and outputs a signal with a high voltage amplitude. The signal line driving circuit receives a lower supply voltage and has a low-threshold transistor. With the above configuration, a signal can be transmitted at a high speed with a low voltage amplitude and low power consumption. Thus, the semiconductor circuit device including the signal line driving circuit can reduce operating current and can be operated with a low amplitude and low standby current at a high speed.
    • 本发明涉及包括逻辑电路和信号线驱动电路的半导体电路器件。 逻辑电路在高电源电压下运行,并输出高电压幅度的信号。 信号线驱动电路接收较低的电源电压并具有低阈值晶体管。 利用上述配置,可以以低电压振幅和低功耗的高速传输信号。 因此,包括信号线驱动电路的半导体电路装置能够降低工作电流,能够以低振幅和低待机电流高速运转。