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41. 发明授权

US08046722B2 Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device 失效
标题翻译：用于校正掩模图案的方法，用于校正掩模图案的系统，程序，用于制造光掩模的方法和用于制造半导体器件的方法
公开(公告)号：US08046722B2
公开(公告)日：2011-10-25
申请号：US12379047
申请日：2009-02-11
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , H01L21/66
CPC分类号： G03F7/70441 , G03F1/36
摘要： A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
摘要翻译：用于校正掩模图案的计算机实现方法包括：通过使用掩模图案来预测设备图案的位移以形成设备图案和处理条件的变化; 确定光学接近校正值，使得位移落在器件图案的位移公差内; 以及使用光学接近校正值来校正掩模图案。

42. 发明授权

US07594216B2 Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask 失效
标题翻译：用于形成掩模图案的方法和系统，制造半导体器件的方法，在数据上形成掩模图案的系统，单元库和形成光掩模的方法
公开(公告)号：US07594216B2
公开(公告)日：2009-09-22
申请号：US10933334
申请日：2004-09-03
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , H01J37/3026 , H01J2237/31769
摘要： A method of forming a mask pattern comprises the following steps. A second cell library is prepared by making process proximity effect correction with respect to cell patterns stored in a first cell library. The second cell library stores corrected cell patterns. A first corrected cell pattern and a second corrected cell pattern of the corrected cell patterns are placed so that an edge of the first corrected cell pattern and an edge of the second corrected cell pattern contact or come close to or overlap each other. A boundary pattern at the boundary neighborhood between the first corrected cell pattern and the second corrected cell pattern is extracted. Process proximity effect correction is made with respect to the boundary pattern.
摘要翻译：形成掩模图案的方法包括以下步骤。通过相对于存储在第一个细胞库中的细胞图案进行过程接近效应校正来制备第二个细胞库。第二个细胞库存储校正的细胞图案。放置经校正的单元图案的第一校正单元图案和第二校正单元图形，使得第一校正单元图案的边缘和第二校正单元图案的边缘彼此接近或重叠。提取在第一校正单元图案和第二校正单元图案之间的边界邻域处的边界图案。相对于边界图案进行过程接近效应校正。

43. 发明授权

US07181707B2 Method of setting process parameter and method of setting process parameter and/or design rule 有权
标题翻译：设置过程参数的方法和设置过程参数和/或设计规则的方法
公开(公告)号：US07181707B2
公开(公告)日：2007-02-20
申请号：US10385628
申请日：2003-03-12
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译：公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

44. 发明授权

US06964031B2 Mask pattern generating method and manufacturing method of semiconductor apparatus 失效
标题翻译：半导体装置的掩模图案生成方法和制造方法
公开(公告)号：US06964031B2
公开(公告)日：2005-11-08
申请号：US10255832
申请日：2002-09-27
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
IPC分类号： H01L21/027 , G03F1/00 , G03F1/36 , G06F17/50 , H01L21/00
CPC分类号： G03F1/36
摘要： A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.
摘要翻译：一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对库和模拟，并使用第二校正库校正设计的模式。

45. 发明授权

US06901577B2 Pattern forming method and semiconductor device manufactured by using said pattern forming method 有权
公开(公告)号：US06901577B2
公开(公告)日：2005-05-31
申请号：US10183572
申请日：2002-06-28
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G03F1/00 , G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , G06F17/50 , G06F9/45
CPC分类号： G03F1/36 , Y10S438/926
摘要： A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.

46. 发明申请

US20090186429A1 Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device 失效
标题翻译：用于校正掩模图案的方法，用于校正掩模图案的系统，程序，用于制造光掩模的方法和用于制造半导体器件的方法
公开(公告)号：US20090186429A1
公开(公告)日：2009-07-23
申请号：US12379047
申请日：2009-02-11
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
摘要翻译：用于校正掩模图案的计算机实现方法包括：通过使用掩模图案来预测设备图案的位移以形成设备图案和处理条件的变化; 确定光学接近校正值，使得位移落在器件图案的位移公差内; 以及使用光学接近校正值来校正掩模图案。

47. 发明授权

US07482661B2 Pattern forming method and semiconductor device manufactured by using said pattern forming method 有权
标题翻译：图案形成方法和使用所述图案形成方法制造的半导体器件
公开(公告)号：US07482661B2
公开(公告)日：2009-01-27
申请号：US11119810
申请日：2005-05-03
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L27/088
CPC分类号： G03F1/36 , Y10S438/926
摘要： A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.
摘要翻译：图案形成方法包括：确定蚀刻转换差的允许值，获得在允许值内产生蚀刻转换差的图案之间的最大距离，包括主图案或两个主图案和虚设图案的图案，准备第一设计布局或者主图案与虚拟图案之间的第二距离小于最大距离的第二设计布局，其中基于第一图案进行设计数据转换，其中，主图案之间的第一距离小于最大距离，或第二设计布局以形成第一或第二设计数据，以及通过使用第一设计数据形成主图案，或者通过使用第二设计数据形成主图案和伪图案。

48. 发明授权

US06180293B2 Mask pattern preparing method and photomask 有权
标题翻译：掩模图案制备方法和光掩模
公开(公告)号：US06180293B2
公开(公告)日：2001-01-30
申请号：US09340148
申请日：1999-06-28
申请人： Satoshi Tanaka , Toshiya Kotani , Soichi Inoue
发明人： Satoshi Tanaka , Toshiya Kotani , Soichi Inoue
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A method for preparing a mask pattern used for forming a desired pattern on a substrate to be exposed comprises the steps of effecting correction on design data in connection with a first element to be corrected, the first element allowing a correction amount to be determined depending upon a pattern contained in an area of a predetermined size, converting the corrected design data to mask writing data, and when write processing is done with a writing device in which mask writing data is incorporated, effecting correction in connection with a second element to be corrected which excludes the first element.
摘要翻译：一种制备用于在待曝光的基板上形成所需图案的掩模图案的方法包括以下步骤：对与待校正的第一元件结合的设计数据进行校正，第一元件允许根据包含在预定尺寸的区域中的图案，将校正后的设计数据转换成掩模写入数据，并且当写入处理是在其中并入掩模写入数据的写入装置完成时，结合要校正的第二元素进行校正排除第一个元素。

49. 发明申请

US20100275174A1 Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法
公开(公告)号：US20100275174A1
公开(公告)日：2010-10-28
申请号：US12801895
申请日：2010-06-30
申请人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
发明人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
摘要翻译：从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。基于第一设计数据计算半导体集成电路的第一特性。通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。基于第二设计数据计算半导体集成电路的第二特性。检查第一特性和第二特性之间的特性差是否落在公差之内。当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。

50. 发明授权

US06907596B2 Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus 失效
标题翻译：掩模数据产生装置，用于产生掩模数据的计算机实现方法和用于控制掩模数据产生装置的计算机程序
公开(公告)号：US06907596B2
公开(公告)日：2005-06-14
申请号：US10385624
申请日：2003-03-12
申请人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe
发明人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , H01L21/027 , H01L21/82 , G06F17/50
CPC分类号： G03F1/36
摘要： A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.
摘要翻译：一种掩模数据生成装置，包括：分割模块，被配置为提取线段并将所提取的线段划分成合适的长度; 校正值计算模块，被配置为从每个分割边缘计算校正值计算点; 第一计算中心点计算模块，被配置为设置第一计算的中心点和图案的形状; 第一矩形区域准备模块，被配置为准备第一模拟区域和彼此重叠的多个第一矩形区域; 第二计算中心点计算模块，被配置为获取第二矩形区域，并且基于所述第二矩形区域计算第二计算的中心点; 配置成获取第二模拟区域的第二模拟区域准备模块; 被配置为计算校正值的过程模拟执行模块; 以及配置为准备校正图案的校正图案准备模块。

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