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    • 41. 发明授权
    • Method of designing low-power semiconductor integrated circuit
    • 低功耗半导体集成电路设计方法
    • US07148135B2
    • 2006-12-12
    • US10815690
    • 2004-04-02
    • Mitsutoshi FujitaShuji Kondo
    • Mitsutoshi FujitaShuji Kondo
    • H01L21/44
    • G06F17/505G06F17/5068
    • A branching point on a wire is detected in the layout results S101. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S102 and that of the route without a dummy buffer being inserted are then calculated S103. Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S104. On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S105. Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S106, processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S107.
    • 在布局结果S101中检测到线上的分支点。 然后,计算在分支点S102之后的导线上插入具有虚拟缓冲器的路径的延迟量和未插入虚拟缓冲器的路线的延迟量。 基于延迟量,确定插入加载分割缓冲器的插入点S 104。 在插入点插入加载分割缓冲器的情况下,计算出插入点之前的驱动单元的驱动能力,使得时序约束得到满足S105。 然后,在确定了在确定的插入点S106上插入负载分配缓冲器之后,对布局结果执行放置加载分割缓冲器,改变驱动单元的驱动能力以及改变布线信息的处理 S 107。