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41. 发明授权

US06771553B2 Low power auto-refresh circuit and method for dynamic random access memories 失效
标题翻译：低功耗自动刷新电路和动态随机存取存储器的方法
公开(公告)号：US06771553B2
公开(公告)日：2004-08-03
申请号：US10056935
申请日：2001-10-18
申请人： Timothy B. Cowles , Brian M. Shirley , Greg A. Blodgett
发明人： Timothy B. Cowles , Brian M. Shirley , Greg A. Blodgett
IPC分类号： G11C700
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40615 , G11C2211/4065 , G11C2211/4067
摘要： A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.
摘要翻译：在DRAM的自动刷新期间，省电电路禁用用于命令和地址信号的输入缓冲器。输入缓冲区在自动刷新结束时以不会导致生成伪指令的方式重新启用。只要禁止命令信号的输入缓冲器，省电电路就可以通过将内部命令信号偏置为“无操作”命令来防止伪指令。 DRAM也可以被置于在自动刷新结束时自动转换到低功率预充电模式的模式，以进一步降低由DRAM消耗的功率。

42. 发明授权

US06674680B2 Methods of programming and circuitry for a programmable element 有权
标题翻译：编程方法和可编程元件的电路
公开(公告)号：US06674680B2
公开(公告)日：2004-01-06
申请号：US10322681
申请日：2002-12-17
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/16 , G11C2207/105
摘要： As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.
摘要翻译：作为用于存储器件的反熔丝电路的一部分，本发明的优选示例性实施例提供了用于向该抗熔丝提供电压的反熔丝和接触焊盘之间的直接连接。接触垫还用作存储器件的至少另一部分的电压源。在存在于焊盘处的电压会损坏电路或导致电路不正确地读取反熔丝的状态的情况下，耦合到反熔丝的至少一个电路与其暂时隔离。接触垫在进程内存储器件的探针级期间可用，但一旦器件被封装，则可以防止接触该接触垫。在生产过程的后端，可以通过第二焊盘访问抗熔丝，其中第二焊盘与抗熔丝进行电连接。

43. 发明授权

US06545510B1 Input buffer and method for voltage level detection 有权
标题翻译：输入缓冲器和电压检测方法
公开(公告)号：US06545510B1
公开(公告)日：2003-04-08
申请号：US10016513
申请日：2001-12-10
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： H03K522
CPC分类号： H03K5/08 , G01R19/16519 , G01R19/16557 , G01R19/16595 , G01R31/30 , G01R31/31721
摘要： An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements. In addition, the input buffer can provide for multiple operations from the same die pad without requiring the addition of command pins.
摘要翻译：提供了一种改进的输入缓冲电路和配置用于电压检测的方法，其可以便于使用中级电压进行测试。配置用于电压检测的示例性输入缓冲器包括参考发生器和多状态检测器。参考发生器被配置为产生要作为输入信号提供给多状态检测器的至少两个参考电压。多状态检测器被适当地配置为接收输入参考信号，并且通过将输入参考信号与两个参考电压进行比较，将输出信号提供给表示高，低和中等级操作状态的三个输出端子。示例性输入缓冲器电路可以包括以背对背布置配置并共享公共节点的两个差分对晶体管，从而导致较低的电流要求。此外，输入缓冲器可以提供来自相同管芯焊盘的多个操作，而不需要添加命令引脚。

44. 发明授权

US06535439B2 Full stress open digit line memory device 有权
标题翻译：全压开路数位线存储器
公开(公告)号：US06535439B2
公开(公告)日：2003-03-18
申请号：US09850792
申请日：2001-05-08
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C29/12 , G11C11/4074 , G11C11/4097 , G11C11/4099
摘要： An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
摘要翻译：开放数字线存储器件包括存储器阵列。存储器阵列包括多个存储单元。存储单元被分组成子阵列。每个子阵列包括多个数字线。来自相邻子阵列的数字线连接到多个读出放大器。位于存储器阵列边缘旁边的读出放大器连接到虚拟数字线。在正常模式期间，虚拟数字线连接到固定电压。在测试模式期间，固定电压由可变电压代替，使得包括边缘处的子阵列的所有子阵列在测试模式期间可以同样受到应力。

45. 发明授权

US06483762B1 tRCD margin 有权
公开(公告)号：US06483762B1
公开(公告)日：2002-11-19
申请号：US10126413
申请日：2002-04-19
申请人： Brendan N. Protzman , Timothy B. Cowles
发明人： Brendan N. Protzman , Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C11/409 , G11C7/1018 , G11C7/1072 , G11C7/22
摘要： A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

46. 发明授权

US06278648B1 Method for writing to multiple banks of a memory device 有权
标题翻译：写入存储器设备的多个组的方法
公开(公告)号：US06278648B1
公开(公告)日：2001-08-21
申请号：US09546683
申请日：2000-04-10
申请人： Timothy B. Cowles , Jeffrey P. Wright
发明人： Timothy B. Cowles , Jeffrey P. Wright
IPC分类号： G11C800
CPC分类号： G11C11/406 , G11C7/1015 , G11C7/1072 , G11C8/12 , G11C11/40611 , G11C11/40615 , G11C29/26 , G11C2029/2602
摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.
摘要翻译：在诸如同步动态随机存取存储器（SDRAM）的多存储体存储器系统中，提供了将数据写入存储体的方法。这种方法允许写入任意数量的银行。更具体地说，这种方法允许写入一个和所有银行之间的选定数量的银行。此外，该方法通过允许每个存储体中的任何行被访问而保留所选存储体的离散性质，而不管其他存储体中激活的行如何。因此，为了将数据写入测试和非测试模式的目的，可以同时访问旨在存储类似数据的不同存储体的行。这允许更快地写入SDRAM，而不会由其他快速写入模式（如数据压缩）创建的错误。

47. 发明授权

US06212114B1 Methods of identifying defects in an array of memory cells and related integrated circuitry 有权
标题翻译：识别存储器单元和相关集成电路阵列中的缺陷的方法
公开(公告)号：US06212114B1
公开(公告)日：2001-04-03
申请号：US09587105
申请日：2000-06-01
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/401
摘要： Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0n, D0n*, where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells. A defect-identifying condition is imposed on the array by placing the cell plate into a first test state, and, using the write circuitry, placing both of the input lines into a common second test state which is different from the first test state.
摘要翻译：描述了识别存储器单元阵列和相关集成电路中的缺陷的方法。在一个实施例中，提供具有多个互补数字线对的存储器单元阵列。数字线对包括各个数字线D0n，D0n *，其中n> 1。互补数字线对被配置为在阵列的感测操作期间被置于不同的状态。通过将至少一个数字线对的两条数字线驱动到公共测试状态，并且使用仅一条专用总线的单元板进行另一种不同的测试状态，将一个缺陷识别信号施加到阵列。在另一个实施例中，提供一对存储单元，每个存储单元具有存取晶体管和电容器。电容器有一个单元板。写电路通过各自的输入线与一对存储单元可操作地耦合。写入电路被配置为将数据写入存储器单元。通过将单元板置于第一测试状态，并且使用写入电路将两个输入线放置在与第一测试状态不同的公共第二测试状态下，对阵列施加缺陷识别条件。

48. 发明授权

US6094388A Methods of identifying defects in an array of memory cells and related integrated circuitry 有权
标题翻译：识别存储器单元和相关集成电路阵列中的缺陷的方法
公开(公告)号：US6094388A
公开(公告)日：2000-07-25
申请号：US346370
申请日：1999-07-01
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0.sub.n, D0.sub.n.sup..cndot., where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells. A defect-identifying condition is imposed on the array by placing the cell plate into a first test state, and, using the write circuitry, placing both of the input lines into a common second test state which is different from the first test state.
摘要翻译：描述了识别存储器单元阵列和相关集成电路中的缺陷的方法。在一个实施例中，提供具有多个互补数字线对的存储器单元阵列。数字线对包括各自的数字线D0n，D0n。，其中n> 1。互补数字线对被配置为在阵列的感测操作期间被置于不同的状态。通过将至少一个数字线对的两条数字线驱动到公共测试状态，并且使用仅一条专用总线的单元板进行另一种不同的测试状态，将一个缺陷识别信号施加到阵列。在另一个实施例中，提供一对存储单元，每个存储单元具有存取晶体管和电容器。电容器有一个单元板。写电路通过各自的输入线与一对存储单元可操作地耦合。写入电路被配置为将数据写入存储器单元。通过将单元板置于第一测试状态，并且使用写入电路将两个输入线放置在与第一测试状态不同的公共第二测试状态下，对阵列施加缺陷识别条件。

49. 发明授权

US5663658A Low current redundancy fuse assembly 失效
标题翻译：低电流冗余保险丝组件
公开(公告)号：US5663658A
公开(公告)日：1997-09-02
申请号：US631449
申请日：1996-04-12
申请人： Timothy B. Cowles , Steven G. Renfro
发明人： Timothy B. Cowles , Steven G. Renfro
IPC分类号： G11C29/00 , H03K19/003 , H03K19/173
CPC分类号： G11C29/787 , G11C29/83 , G11C29/832 , H03K19/00392 , H03K19/1736
摘要： In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programing circuits, and by adding a second fuse into each programming circuit; whereby, the bank of programming circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programing logic can be set by alternately blowing one of its pair of fuses, thus cutting off any current path through the programming circuit regardless of the programming state of the circuit.
摘要翻译：在诸如存储器芯片的微电路设备中，其中使用一组熔丝控制的锁存脉冲路由选择电路来编程具有每个存储器周期或其多个的冗余电路或其他编程选项，每个熔丝控制所绘制的电流量通过在锁存脉冲源和熔丝控制的编程电路组之间通过控制具有可使能的熔丝编程电路的每个电路组减少电路，并且通过在每个编程电路中添加第二熔丝; 由此，可以通过交替地在组使能电路中吹送两个熔丝中的一个来实现编程电路组，并且可以通过交替地吹送其一对熔丝之一来设置每个编程逻辑，从而通过编程切断任何当前路径电路与电路的编程状态无关。

50. 发明授权

US5508638A Low current redundancy fuse assembly 失效
标题翻译：低电流冗余保险丝组件
公开(公告)号：US5508638A
公开(公告)日：1996-04-16
申请号：US452203
申请日：1995-05-26
申请人： Timothy B. Cowles , Steven G. Renfro
发明人： Timothy B. Cowles , Steven G. Renfro
IPC分类号： G11C29/00 , H03K19/003 , H03K19/173
CPC分类号： G11C29/787 , G11C29/83 , G11C29/832 , H03K19/00392 , H03K19/1736
摘要： In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programing circuits, and by adding a second fuse into each programing circuit; whereby, the bank of programming circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programing circuit regardless of the programing state of the circuit.
摘要翻译：在诸如存储器芯片的微电路设备中，其中使用一组熔丝控制的锁存脉冲路由选择电路来编程具有每个存储器周期或其多个的冗余电路或其他编程选项，每个熔丝控制所绘制的电流量通过在锁存脉冲源和熔丝控制的编程电路组之间通过使用可使能熔丝编程的电路来控制每个电路组，并且通过在每个编程电路中添加第二个熔丝来减少电路; 由此，编程电路组可以通过交替地在组使能电路中吹送两个熔丝中的一个来实现，并且每个编程逻辑可以通过交替地吹送其一对熔丝中的一个来设置，从而切断通过编程电路的任何电流路径，而不管的电路编程状态。

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