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41. 发明申请

US20130040438A1 EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
标题翻译：首先使用HCl / GeH4 / H2SiCl2表面清洁的外延工艺
公开(公告)号：US20130040438A1
公开(公告)日：2013-02-14
申请号：US13206248
申请日：2011-08-09
申请人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
发明人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
IPC分类号： H01L21/205 , H01L21/322
CPC分类号： H01L21/0237 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661
摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
摘要翻译：一种沉积外延层的方法，包括化学清洗半导体衬底的沉积表面，并在预烘烤温度下用含氢气体处理半导体衬底的沉积表面。含氢气体处理可以在外延沉积室中进行。含氢气体从半导体衬底的沉积表面去除含氧材料。然后可以用包含至少一种盐酸（HCl），锗烷（GeH4）和二氯硅烷（H 2 SiCl 2））的气流来处理半导体衬底的沉积表面，该气流随着温度从预烘烤温度达到外延沉积温度。可以将至少一种源气体施加到沉积表面，用于材料层的外延沉积。

42. 发明授权

US08039351B2 Method of fabricating hetero-junction bipolar transistor (HBT) 有权
标题翻译：异质结双极晶体管（HBT）的制造方法
公开(公告)号：US08039351B2
公开(公告)日：2011-10-18
申请号：US12732560
申请日：2010-03-26
申请人： Thomas N. Adam , Rajendran Krishnasamy
发明人： Thomas N. Adam , Rajendran Krishnasamy
IPC分类号： H01L21/8222
CPC分类号： H01L29/7371 , H01L21/82285 , H01L21/823878 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0826 , H01L27/1203 , H01L29/045
摘要： A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation in addition to silicon crystalline orientation to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation may be disposed on crystalline orientation . Alternatively, the region of silicon crystalline orientation may be disposed on crystalline orientation .
摘要翻译：公开了一种制造异质结双极晶体管（HBT）的方法，其中HBT具有结合设置在包含硅晶取向<110>的衬底上的异质结双极结构的结构。异质结双极结构可以包括发射极，基极和集电极。衬底可以包括浅沟槽隔离（STI）区域和设置有集电极的深沟槽区域。除了硅晶体取向<110>之外，衬底可以包括硅晶体取向<100>的区域，以通过使用混合取向技术（HOT）形成复合衬底。结晶取向区域<100>可以设置在晶体取向110上。或者，硅结晶取向区域<110>可以以结晶取向<100>设置。

43. 发明申请

US20100208869A1 MEASURING STRAIN OF EPITAXIAL FILMS USING MICRO X-RAY DIFFRACTION FOR IN-LINE METROLOGY 失效
标题翻译：使用微型X射线衍射测量外延膜的应变在线计量
公开(公告)号：US20100208869A1
公开(公告)日：2010-08-19
申请号：US12372104
申请日：2009-02-17
申请人： Thomas N. Adam , Eric C. Harley , Anita Madan , Teresa L. Pinto
发明人： Thomas N. Adam , Eric C. Harley , Anita Madan , Teresa L. Pinto
IPC分类号： G01N23/20 , G06F17/00
CPC分类号： G01N23/20 , G01N2223/6116
摘要： In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest
摘要翻译：在使用x射线衍射测量SOI衬底的顶部硅锗层上的应变的方法中，SOI衬底的上硅层的峰值衍射面积的位置是通过首先确定峰值衍射面积在半导体晶片上形成的晶片内的参考焊盘（其中SOI厚度为约700-900埃）上硅层。 X射线束然后移动到要测量的感兴趣的焊盘上的该位置，并且在感兴趣的焊盘上开始XRD扫描，以最终确定感兴趣焊盘顶部硅锗层的应变

44. 发明申请

US20100178746A1 METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) 有权
标题翻译：制备异相双极晶体管（HBT）的方法
公开(公告)号：US20100178746A1
公开(公告)日：2010-07-15
申请号：US12732560
申请日：2010-03-26
申请人： Thomas N. Adam , Rajendran Krishnasamy
发明人： Thomas N. Adam , Rajendran Krishnasamy
IPC分类号： H01L21/8222
CPC分类号： H01L29/7371 , H01L21/82285 , H01L21/823878 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0826 , H01L27/1203 , H01L29/045
摘要： A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation in addition to silicon crystalline orientation to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation may be disposed on crystalline orientation . Alternatively, the region of silicon crystalline orientation may be disposed on crystalline orientation .
摘要翻译：公开了一种制造异质结双极晶体管（HBT）的方法，其中HBT具有结合设置在包含硅晶取向<110>的衬底上的异质结双极结构的结构。异质结双极结构可以包括发射极，基极和集电极。衬底可以包括浅沟槽隔离（STI）区域和设置有集电极的深沟槽区域。除了硅晶体取向<110>之外，衬底可以包括硅晶体取向<100>的区域，以通过使用混合取向技术（HOT）形成复合衬底。结晶取向区域<100>可以设置在晶体取向110上。或者，硅结晶取向区域<110>可以以结晶取向<100>设置。

45. 发明申请

US20090224286A1 MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS 审中-公开
标题翻译： SiGe异相双极晶体管中的移动增强
公开(公告)号：US20090224286A1
公开(公告)日：2009-09-10
申请号：US12469980
申请日：2009-05-21
申请人： Thomas N. Adam , Dureseti Chidambarrao
发明人： Thomas N. Adam , Dureseti Chidambarrao
IPC分类号： H01L29/737
CPC分类号： H01L29/7378 , H01L29/161 , H01L29/165
摘要： The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.
摘要翻译：本发明涉及在其中具有含SiGe的层的基极区域的高性能异质结双极晶体管（HBT）。含SiGe的层的厚度不超过约100nm，具有预定的临界锗含量。含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量。本发明还涉及通过均匀地提高基底层中的锗含量，使其中的平均锗含量不低于临界锗含量的80％，来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法，其基于基底层的厚度计算，条件是基底层不大于100nm厚。

46. 发明授权

US07544577B2 Mobility enhancement in SiGe heterojunction bipolar transistors 失效
标题翻译： SiGe异质结双极晶体管中的迁移增强
公开(公告)号：US07544577B2
公开(公告)日：2009-06-09
申请号：US11212187
申请日：2005-08-26
申请人： Thomas N. Adam , Dureseti Chidambarrao
发明人： Thomas N. Adam , Dureseti Chidambarrao
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/161 , H01L29/165
摘要： The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.
摘要翻译：本发明涉及在其中具有含SiGe的层的基极区域的高性能异质结双极晶体管（HBT）。含SiGe的层的厚度不超过约100nm，具有预定的临界锗含量。含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量。本发明还涉及通过均匀地提高基底层中的锗含量，使其中的平均锗含量不低于临界锗含量的80％，来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法，其基于基底层的厚度计算，条件是基底层不大于100nm厚。

47. 发明申请

US20080179632A1 SELECTIVE LINKS IN SILICON HETERO-JUNCTION BIPOLAR TRANSISTORS USING CARBON DOPING AND METHOD OF FORMING SAME 有权
标题翻译：使用碳掺杂的硅异质结双极晶体管中的选择性链接及其形成方法
公开(公告)号：US20080179632A1
公开(公告)日：2008-07-31
申请号：US12060615
申请日：2008-04-01
申请人： Thomas N. Adam , Rajendran Krishnasamy
发明人： Thomas N. Adam , Rajendran Krishnasamy
IPC分类号： H01L29/737
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242
摘要： Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.
摘要翻译：双极晶体管和形成双极晶体管的方法。该方法包括在硅衬底中形成P型集电体; 在集电体上形成本征碱，本征碱包括第一N型掺杂剂物质，锗和碳; 在本征基极的第一区域和第二区域上形成N型外部基极，在与集电体相邻的电介质上的集电极和第二区域之上的第一区域，含有或不含有碳的N型外部碱基; 以及在本征基底的第一区域上形成P型发射体。

48. 发明授权

US09059207B2 Strained channel for depleted channel semiconductor devices 有权
标题翻译：用于耗尽通道半导体器件的应变通道
公开(公告)号：US09059207B2
公开(公告)日：2015-06-16
申请号：US13613747
申请日：2012-09-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
摘要翻译：一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层的多层应变通道部分。功能栅极结构存在于SOI衬底的多层应变通道部分上。具有多层通道的半导体器件也可以是finFET半导体器件。

49. 发明授权

US08946033B2 Merged fin finFET with (100) sidewall surfaces and method of making same 有权
标题翻译：具有（100）侧壁表面的合并翅片finFET及其制造方法
公开(公告)号：US08946033B2
公开(公告)日：2015-02-03
申请号：US13561352
申请日：2012-07-30
申请人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L29/16 , H01L29/161 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795
摘要： A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.
摘要翻译：翅片finFET和其制造方法。鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

50. 发明授权

US08728897B2 Power sige heterojunction bipolar transistor (HBT) with improved drive current by strain compensation 有权
标题翻译：功率奇异异质结双极晶体管（HBT）通过应变补偿提高驱动电流
公开(公告)号：US08728897B2
公开(公告)日：2014-05-20
申请号：US13342797
申请日：2012-01-03
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L29/66242 , H01L21/76232 , H01L22/20 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/7371
摘要： A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer.
摘要翻译：提供了通过应变补偿和制造方法提高驱动电流的功率SiGe异质结双色晶体管（HBT）。一种方法包括在包括子集电极层，集电极层，基极缓冲层，基极层和发射极缓冲层的器件的层中以连续稳定的浓度添加碳。

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