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41. 发明申请

US20120286987A1 AD CONVERTER AND TD CONVERTER CONFIGURED WITHOUT OPERATIONAL AMPLIFIER AND CAPACITOR 失效
标题翻译： AD转换器和TD转换器配置无运算放大器和电容器
公开(公告)号：US20120286987A1
公开(公告)日：2012-11-15
申请号：US13470605
申请日：2012-05-14
申请人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
发明人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , H03M3/416
摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环振荡电路是后续阶段的一部分。计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。

42. 发明授权

US08238140B2 Semiconductor memory and program 有权
标题翻译：半导体存储器和程序
公开(公告)号：US08238140B2
公开(公告)日：2012-08-07
申请号：US12809684
申请日：2009-01-07
申请人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Shunsuke Okumura , Hidehiro Fujiwara
发明人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Shunsuke Okumura , Hidehiro Fujiwara
IPC分类号： G11C11/24 , G11C11/00 , G11C7/00 , G11C7/02 , G11C29/00
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.
摘要翻译：可以根据应用或存储器状态来动态地改变存储器单元的位可靠性的存储器，从而确保操作稳定性，从而实现低功耗和高可靠性。一个位由一个存储器单元组成的模式（1位/ 1单元模式）或其中一个位由n组成的模式（1位/ n单元模式）或更多）连接的存储器单元被动态地选择。当选择1位/ n单元模式时，增加了一位的读/写稳定性，读取期间的单元电流增加（读取速度加快），如果出现位错误，则自校正。特别地，在n个相邻的存储单元的数据保持节点之间添加一对CMOS晶体管和用于执行控制以允许CMOS晶体管导通的控制线。由此，对字线（WL）进行控制，从而进一步提高操作稳定性。

43. 发明申请

US20100292987A1 CIRCUIT STARTUP METHOD AND CIRCUIT STARTUP APPARATUS UTILIZING UTTERANCE ESTIMATION FOR USE IN SPEECH PROCESSING SYSTEM PROVIDED WITH SOUND COLLECTING DEVICE 审中-公开
标题翻译：电路启动方法和电路启动装置使用用于使用声音收集装置提供的语音处理系统中的使用估计
公开(公告)号：US20100292987A1
公开(公告)日：2010-11-18
申请号：US12774923
申请日：2010-05-06
申请人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Hiroki Noguchi , Tomoya Takagi
发明人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Hiroki Noguchi , Tomoya Takagi
IPC分类号： G10L15/20
CPC分类号： G10L25/78 , G10L15/28
摘要： A circuit startup method utilizing utterance estimation in a speech processing system including a sound collecting device is provided. The circuit startup method includes a subset power supply step of supplying power to the sound collecting device and a signal processing circuit, and a sound collecting step of inputting a sound from the sound collecting device through the signal processing circuit. The circuit startup method further includes an utterance estimation step of estimating whether or not a speech is contained in the inputted sound, and a power supply step of supplying power to the speech processing circuit for an utterance interval when it is estimated that a speech is contained from an estimation result of the utterance estimation step.
摘要翻译：提供一种在包括声音采集装置的语音处理系统中利用话语估计的电路启动方法。电路启动方法包括向收音装置供电的子集电源步骤和信号处理电路，以及通过信号处理电路从声音采集装置输入声音的声音采集步骤。电路启动方法还包括：估计语音是否包含在输入声音中的话语估计步骤;以及当估计出包含语音时，向语音处理电路供给话音间隔的电力供给步骤根据话语估计步骤的估计结果。

44. 发明申请

US20090034620A1 MOTION ESTIMATION METHOD 审中-公开
标题翻译：运动估计方法
公开(公告)号：US20090034620A1
公开(公告)日：2009-02-05
申请号：US12088303
申请日：2006-06-29
申请人： Mayumi Okumura , Masaki Hamamoto , Yuichiro Murachi , Junichi Miyakoshi , Masahiko Yoshimoto , Tetsuro Matsuno
发明人： Mayumi Okumura , Masaki Hamamoto , Yuichiro Murachi , Junichi Miyakoshi , Masahiko Yoshimoto , Tetsuro Matsuno
IPC分类号： H04N7/26
CPC分类号： H04N19/53
摘要： A motion estimation method capable of reducing the amount of calculation as compared to a full search method. In the method, a coarse search block and fine search blocks are defined. The fine search blocks are given by dividing the coarse search block into a plurality of blocks so that the fine search blocks are contained in the coarse search block. A sparsely interpolated image and a densely interpolated image are defined. A first search is performed using the defined coarse search block and the defined sparsely interpolated image. A second search is performed using the defined coarse search block and the defined densely interpolated image. With regard to search blocks belonging to the fine search blocks, only a surrounding region of an optimal point obtained in the first search is searched.
摘要翻译：一种与全搜索方法相比能够减少计算量的运动估计方法。在该方法中，定义了粗搜索块和精细搜索块。精细搜索块通过将粗略搜索块划分成多个块来给出，使得精细搜索块被包含在粗略搜索块中。定义了稀疏内插图像和密集内插图像。使用定义的粗略搜索块和定义的稀疏内插图像来执行第一搜索。使用定义的粗略搜索块和所定义的密集内插图像来执行第二次搜索。关于属于精细搜索块的搜索块，仅搜索在第一搜索中获得的最佳点的周围区域。

45. 发明授权

US06237023B1 System for controlling the authority of a terminal capable of simultaneously operating a plurality of client softwares which transmit service requests 失效
标题翻译：用于控制能够同时操作传送服务请求的多个客户端软件的终端的权限的系统
公开(公告)号：US06237023B1
公开(公告)日：2001-05-22
申请号：US08873104
申请日：1997-06-11
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
IPC分类号： G06F1516
CPC分类号： H04L63/102
摘要： When a server receives a service request from a client, identifiers of a terminal and of a user are acquired from the service request and authority with respect to the service request is uniquely decided from the terminal and user identifiers acquired. It is then determined, using the authority decided, whether or not to accept the service request.
摘要翻译：当服务器从客户端接收到服务请求时，从服务请求获得终端和用户的标识符，并且从终端和所获得的用户标识符唯一地确定关于服务请求的权限。然后，使用所决定的权限确定是否接受服务请求。

46. 发明授权

US6148299A Selectively processing plurality of transactions using transaction identifiers that including committing, aborting updating and continuous updating content in a plurality of shared data 失效
标题翻译：使用包括在多个共享数据中提交，中止更新和连续更新内容的事务标识符来选择性地处理多个事务
公开(公告)号：US6148299A
公开(公告)日：2000-11-14
申请号：US873712
申请日：1997-06-12
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
IPC分类号： G06F12/00 , G06F9/46 , G06F17/30
CPC分类号： G06F9/466 , Y10S707/99938 , Y10S707/99953
摘要： An information processing apparatus manages the correspondence between identification information, which is for identifying a plurality of transactions within one process, and the transactions. To this end, the information processing apparatus operates on the identification information by operations including creation, cancellation and switching of the identification information. The creation, cancellation and switching of the identification information then results in the corresponding operation on the respective transaction.
摘要翻译：信息处理装置管理用于识别一个进程内的多个事务的识别信息与事务之间的对应关系。为此，信息处理装置通过包括识别信息的创建，取消和切换的操作对识别信息进行操作。识别信息的创建，取消和切换导致相应的交易的相应操作。

47. 发明授权

US4876610A Image processing apparatus with binarization-error dispersal 失效
标题翻译：具有二值化误差分散的图像处理装置
公开(公告)号：US4876610A
公开(公告)日：1989-10-24
申请号：US137439
申请日：1987-12-23
申请人： Hidefumi Ohsawa , Akihiro Katayama , Hiroshi Hosokawa , Izuru Sunohara , Masahiko Yoshimoto
发明人： Hidefumi Ohsawa , Akihiro Katayama , Hiroshi Hosokawa , Izuru Sunohara , Masahiko Yoshimoto
IPC分类号： G06K9/38 , H04N1/405 , H04N1/52
CPC分类号： H04N1/52 , G06K9/38 , H04N1/4052 , G06K2209/01
摘要： An image processing apparatus for digitizing an analog image by dispersing the digitizing error to the surrounding areas. The characteristics or edge of the analog image are identified, and the error dispersing area is varied according to the result of identification, thus enabling reproduction of the image with high quality regardless of the nature of the original image.
摘要翻译：一种图像处理装置，用于通过将数字化误差分散到周围区域来数字化模拟图像。识别模拟图像的特征或边缘，并且根据识别结果改变误差分散区域，从而能够以高质量再现图像，而与原始图像的性质无关。

48. 发明授权

US4849937A Digital delay unit with interleaved memory 失效
标题翻译：具有交错存储器的数字延迟单元
公开(公告)号：US4849937A
公开(公告)日：1989-07-18
申请号：US169066
申请日：1988-03-17
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
IPC分类号： G11C7/00 , G11C7/10 , G11C8/04 , H04N5/907
CPC分类号： H04N5/907 , G11C7/00 , G11C7/1042 , G11C7/1075 , G11C8/04
摘要： A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.
摘要翻译：第一存储单元阵列（84）具有偶数地址空间，第二存储单元阵列94具有奇数地址空间。存储单元阵列（84,94）由从地址计数器（81）产生的偶数地址信号和从地址计数器（91）产生的奇数地址信号交替访问，使得存储在存储单元阵列中的数据被交替地读取，新的输入数据被写入访问的存储单元。

49. 发明授权

US4606013A Redundancy-secured semiconductor memory 失效
标题翻译：冗余半导体存储器
公开(公告)号：US4606013A
公开(公告)日：1986-08-12
申请号：US579604
申请日：1984-02-13
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
IPC分类号： G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/789 , G11C29/832
摘要： A redundancy-secured semiconductor memory including a matrix of regular memory cells consisting of a plurality of regular memory cell trains, an extra memory cell train for redundant construction, and a taking-over system for enabling the extra memory cell train to take over the function of a faulty regular memory cell train including a faulty bit, wherein the taking-over system comprises a decoder and a monostable latching circuit connected to the decoder through a current conducting element capable of breakage in response to when one of the regular memory cell trains comes to include a faulty bit, thereby enabling the monostable latching circuit to fix its output to the low logic potential. Thus, the faulty regular memory cell train is kept in an unselected state without DC power consumption.
摘要翻译：一种冗余保护半导体存储器，包括由多个常规存储单元列组成的常规存储器单元矩阵，用于冗余结构的额外存储单元串，以及用于使额外存储单元串能够接管功能的接管系统包括故障位的故障常规存储器单元串，其中，所述接收系统包括解码器和单稳态锁存电路，所述解调器和单稳态锁存电路通过电流传导元件连接到所述解码器，所述电流导电元件响应于当所述常规存储器单元列中的一个来自以包括故障位，从而使单稳态锁存电路将其输出固定为低逻辑电位。因此，故障的常规存储器单元串在没有DC功率消耗的情况下保持在未选择状态。

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