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41. 发明授权

US06930057B2 Columnar structured material and manufacturing method therefor 失效
标题翻译：柱状结构材料及其制造方法
公开(公告)号：US06930057B2
公开(公告)日：2005-08-16
申请号：US10744390
申请日：2003-12-23
申请人： Tatsuya Saito , Tohru Den
发明人： Tatsuya Saito , Tohru Den
IPC分类号： G11B5/65 , C25D11/16 , G11B5/74 , G11B5/82 , G11B5/84 , G11B5/855 , G11B5/858 , H01L21/31 , B05D3/00 , H01L21/461
CPC分类号： C25D11/16 , B82Y10/00 , G11B5/74 , G11B5/743 , G11B5/82 , G11B5/8404 , G11B5/855 , G11B5/858
摘要： To provide a method for manufacturing a magnetic recording medium which creates anodically oxidized aluminum nanoholes so as to have a rectangular or elliptical sectional shape and gives shape anisotropy to a magnetic material filled in the nanoholes to thereby always fix a relative positional relation between magnetizations of the magnetic material and a magnetic head that detects the magnetizations. The method for manufacturing a magnetic recording medium includes: preparing a member having regularly arranged plural pits; subjecting the member to anodic oxidation treatment so that formation of holes is started with the pits as starting points, and a porous region, which has a first portion where the holes are formed without branching and a second portion where branched holes are formed, is formed; filling a magnetic material in the formed holes; and removing the non-branching portions of the holes.
摘要翻译：为了提供一种制造磁记录介质的方法，该磁记录介质产生阳极氧化的铝纳米孔，从而具有矩形或椭圆形截面形状，并且对填充在该纳米孔中的磁性材料赋予形状各向异性，从而总是将相对位置关系固定在磁性材料和检测磁化的磁头。制造磁记录介质的方法包括：制备具有规则排列的多个凹坑的构件; 对构件进行阳极氧化处理，以便以凹坑为起点开始孔的形成，并且形成有多孔区域，其具有不分支形成孔的第一部分和形成有分支孔的第二部分 ; 在形成的孔中填充磁性材料; 并且去除所述孔的非分支部分。

42. 发明申请

US20050120057A1 Information processing device for managing data storage and method of data management 审中-公开
标题翻译：用于管理数据存储的信息处理设备和数据管理方法
公开(公告)号：US20050120057A1
公开(公告)日：2005-06-02
申请号：US10984987
申请日：2004-11-10
申请人： Hirobumi Hashimoto , Koichi Ishii , Tetsuji Ohno , Tatsuya Saito , Masahiro Nagakura , Katsuya Yokomura
发明人： Hirobumi Hashimoto , Koichi Ishii , Tetsuji Ohno , Tatsuya Saito , Masahiro Nagakura , Katsuya Yokomura
IPC分类号： G06Q50/10 , G06F12/00 , G06Q50/00
CPC分类号： G06Q30/00
摘要： The cost of service provision for data storage is minimized, particularly for temporary storage of data. An information processing device includes: a storage case searching unit that accepts a data storage request from an input interface and searches cases in which data can be stored in a data center having a free capacity of at least the size of the storage data, as indicated in the data storage request and a data center table; a storage cost calculation unit that calculates the storage cost required for each case; a default cost calculation unit that calculates the default cost required for each case; and a case selection unit that calculates the total cost for each case and selects whether the data is stored in the data center or whether a data storage request is made to the data center, according to the case for which the total cost is a minimum.
摘要翻译：数据存储的服务提供成本最小化，特别是临时存储数据。信息处理装置包括：存储箱搜索单元，其从输入接口接收数据存储请求，并且搜索数据可以存储在具有至少存储数据的大小的可用容量的数据中心的情况下，如所指示的在数据存储请求和数据中心表中; 存储成本计算单元，计算每种情况所需的存储成本; 默认成本计算单元，计算每种情况所需的默认成本; 以及案例选择单元，根据总成本最小的情况，计算每种情况的总成本，并选择数据是存储在数据中心还是数据存储请求到数据中心。

43. 发明授权

US06813724B2 Phase-controlled source synchronous interface circuit 失效
标题翻译：相控源同步接口电路
公开(公告)号：US06813724B2
公开(公告)日：2004-11-02
申请号：US09796557
申请日：2001-03-02
申请人： Tatsuya Saito
发明人： Tatsuya Saito
IPC分类号： G06F112
CPC分类号： G06F13/423
摘要： A source synchronous type interface circuit in which, for fetch of a transmitted data, a source synchronous clock indicating a data transmission timing is transmitted from transmission to reception side along with the data, so that a reception clock is generated to define an operation timing of a first reception flip-flop for taking in a data from the reception signal of the source synchronous clock. The interface further includes a second reception flip-flop for feeding an output from the first reception flip-flop further to a second reception flip-flop in synchronization with a common system clock and a variable delay circuit for absorbing phase fluctuations of the first reception flip-flop depending on transmission delay time, to assure a phase difference required for correctly receiving the data. The variable delay circuit has a delay amount automatically controlled according to phase differences between the system clock and the source synchronous clock received.
摘要翻译：一种源同步型接口电路，其中为了获取发送数据，指示数据发送定时的源同步时钟与数据一起从发送发送到接收侧，使得产生接收时钟以定义操作定时用于从源同步时钟的接收信号接收数据的第一接收触发器。该接口还包括第二接收触发器，用于与公共系统时钟同步地向第二接收触发器馈送来自第一接收触发器的输出，以及用于吸收第一接收翻转的相位波动的可变延迟电路 -flop取决于传输延迟时间，以确保正确接收数据所需的相位差。可变延迟电路具有根据系统时钟和接收的源同步时钟之间的相位差自动控制的延迟量。

44. 发明授权

US06655029B2 Safety razor 失效
标题翻译：安全剃须刀
公开(公告)号：US06655029B2
公开(公告)日：2003-12-02
申请号：US09281652
申请日：1999-03-30
申请人： Tatsuya Saito
发明人： Tatsuya Saito
IPC分类号： B26B2140
CPC分类号： B26B21/222
摘要： A safety razor with a plurality of blade members which are covered by a guard plate. The guard plate is provided with a plurality of blade tip guards which are arranged along the blade tip edges of the blade members, and the blade tip edge of at least one of the plurality of blade members is not in contact with the blade tip guards of the guard plate and exposed between the blade tip guards.
摘要翻译：一种具有多个叶片构件的安全剃须刀，其被防护板覆盖。防护板设置有多个叶片护罩，其沿叶片构件的叶片尖端边缘布置，并且多个叶片构件中的至少一个叶片构件的叶片尖端边缘不与叶片前端保护件防护板和刀片护罩之间暴露。

45. 发明授权

US5815007A More-than-one detector 失效
标题翻译：多于一个的检测器
公开(公告)号：US5815007A
公开(公告)日：1998-09-29
申请号：US632391
申请日：1996-04-10
申请人： Tatsuya Saito
发明人： Tatsuya Saito
IPC分类号： H03K19/20 , H03K19/0944 , H03K19/0948 , H03K19/23 , H03K19/094 , H03K19/082
CPC分类号： H03K19/23 , H03K19/0948
摘要： In order to provide a detector with fewer switching elements for detecting simultaneous occurrence of more than one of logic `1` or logic `0` out of plural inputs, 4 inputs A, B, C and D for example, a detector of the invention detects more than one of logic `1` from NAND logic of outputs of 3 OR-NAND composit gates as follows. ##EQU1## Each OR-NAND composit gate is composed of 4 pMOS transistors for common use and 4 nMOS transistors and a NAND gate of 3 inputs is composed of 3 pMOS transistors and 3 nMOS transistors. Therefore, the detector of 4 inputs of the invention can be composed of 22 MOSFETs insted of 36 MOSFETs needed for a conventional detector of 6 NAND gates of 2 inputs and a NAND gate of 6 inputs.
摘要翻译：为了提供具有更少的开关元件的检测器，用于检测多个输入中的逻辑“1”或逻辑“0”的多于一个，例如4个输入A，B，C和D，本发明的检测器从3个OR-NAND复合门的输出的NAND逻辑中检测多个逻辑“1”，如下。 A x B + A x C + A x D + B x C + B x D + C x D = NOT（NOT（A x（B + C + D））+ NOT（（A + B）x（C + D））+ + TR NOT（（A + B + C）×D））每个OR-NAND复合栅极由4个常用的pMOS晶体管和4个nMOS晶体管组成，3个输入的NAND门由3个pMOS 晶体管和3 nMOS晶体管。因此，本发明的4个输入的检测器可以由22个MOSFET构成，其中36个MOSFET是用于2个输入的6个NAND门的常规检测器和6个输入的NAND门所需要的。

46. 发明授权

US5106088A Iron or wood golf club 失效
标题翻译：铁或木高尔夫球杆
公开(公告)号：US5106088A
公开(公告)日：1992-04-21
申请号：US611297
申请日：1990-11-09
申请人： Tatsuya Saito
发明人： Tatsuya Saito
IPC分类号： A63B53/02 , A63B53/00 , A63B53/04
CPC分类号： A63B53/00
摘要： The present invention discloses an iron or wood golf club head 10 designed to strike a golf ball so that it flies straight in a desired direction. The golf club head 10 consists generally of a striking surface 11, including a leading edge 12, and a hosel member 15, which provides a socket for insertion of a shaft member 19. The hosel member 15 extends from the striking surface 11 at a substantially perpendicular angle relative to the leading edge 12.
摘要翻译：本发明公开了一种铁杆或木头高尔夫球杆头10，其被设计成撞击高尔夫球，使得其沿所需方向直线飞行。高尔夫球杆头10大体上由包括前缘12的冲击表面11和插座构件15组成，插头构件15提供用于插入轴构件19的插座。插鞘构件15基本上从击打表面11延伸相对于前缘12的垂直角度。

47. 外观设计

USD242959S Nail clipper 失效
公开(公告)号：USD242959S
公开(公告)日：1977-01-04
申请号：US518177
申请日：1974-10-25
申请人： Tatsuya Saito
设计人： Tatsuya Saito

48. 发明授权

US08445832B2 Optical communication device 有权
标题翻译：光通信设备
公开(公告)号：US08445832B2
公开(公告)日：2013-05-21
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/08 , H01J43/00 , H01J40/14 , G01R19/00
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

49. 发明授权

US08049303B2 Semiconductor device with power noise suppression 失效
标题翻译：具有功率噪声抑制的半导体器件
公开(公告)号：US08049303B2
公开(公告)日：2011-11-01
申请号：US12107758
申请日：2008-04-22
申请人： Hideki Osaka , Tatsuya Saito
发明人： Hideki Osaka , Tatsuya Saito
IPC分类号： H01L45/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/50 , H01L23/642 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/73257 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , Y10S257/904 , Y10S257/924 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.
摘要翻译：一种半导体芯片和半导体器件，其安装半导体芯片能够增加电容器的电容而不减少封装的信号凸块或功率凸块的数量以及半导体芯片的C4焊球的数量，并实现稳定的电源抑制共振频率下的功率波动，而不会在安装用于降低信号收发接口块的噪声的电容器的位置上受到限制。在半导体装置中，在半导体芯片上设置有通孔，在该半导体芯片的背面设有与通路孔连接的电源电极，在背面的电极上安装有电容器。并且，高电阻材料用于半导体芯片内的电源通孔的材料，从而增加电阻并降低Q因子。

50. 发明授权

US08005130B2 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US08005130B2
公开(公告)日：2011-08-23
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

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