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    • 42. 发明授权
    • Semiconductor memory system and signal processing system
    • 半导体存储器系统和信号处理系统
    • US08166371B2
    • 2012-04-24
    • US11984718
    • 2007-11-21
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • H03M13/00
    • G06F11/1068
    • A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.
    • 一种半导体存储器件,其具有用于接收1页数据的数据输入部分,将其划分为多个码字,生成并添加每个码字的校验码(奇偶校验数据),连续形成主码字并传送 以及数据输出部分,用于接收包括从数据锁存电路传送的主码字的1页数据的数据,当存在预定数量的错误数据时校正错误数据 对于每个主代码字,添加用于读取除检查码(奇偶校验数据)之外的每个读取码字的错误信息,并将其传送到主机侧,以及使用该错误信息的信号处理系统。