专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5588130A Semiconductor memory device for simple cache system 失效
公开(公告)号：US5588130A
公开(公告)日：1996-12-24
申请号：US283367
申请日：1994-08-01
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G06F12/08 , G11C7/10 , G06F13/00 , G11C15/00
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

42. 发明授权

US5426615A Semiconductor memory device having power line arranged in a meshed shape 失效
标题翻译：具有布置成网状的电力线的半导体存储器件
公开(公告)号：US5426615A
公开(公告)日：1995-06-20
申请号：US224461
申请日：1994-04-07
申请人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka
发明人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka
IPC分类号： G11C5/14 , G11C7/06 , G11C5/02
CPC分类号： G11C7/06 , G11C5/14
摘要： A semiconductor memory device includes a sense amp band comprising a plurality of sense amplifiers, and a plurality of power supply and ground lines arranged in a meshed shape. Power supply and ground lines include lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to a power supply and ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. Each drive component is provided for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of power supply and ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potential is generated to allow a stable supply of a power supply and ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to proximate power supply and ground lines through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.
摘要翻译：半导体存储器件包括包括多个读出放大器的检测放大器带以及以网状形状布置的多个电源和接地线。电源和接地线包括与感测放大器带平行并接近的线。感测放大器频带中的每个读出放大器通过驱动部件连接到布置在感测放大器附近并与其平行布置的电源和接地线。每个驱动部件被提供用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。布置成网状的多个电源和接地线在交叉点处接触。因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源和接地电位。此外，由于读出放大器通过驱动部件连接到邻近的电源和接地线，所以无论感测放大器驱动信号线的长度如何，都可以进行可靠且高速的感测操作。

43. 发明授权

US5321646A Layout of a semiconductor memory device 失效
标题翻译：半导体存储器件的布局
公开(公告)号：US5321646A
公开(公告)日：1994-06-14
申请号：US865142
申请日：1992-04-08
申请人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi
发明人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi
IPC分类号： G11C11/409 , G11C5/14 , G11C7/06 , G11C11/401 , G11C11/4074 , G11C5/02 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C7/065
摘要： A power supply line is disposed parallel to a sense amplifier train including a plurality of sense amplifiers at the side of each subarray. The power supply line is connected to the sense amplifier included in the sense amplifier train via a plurality of drive transistors and a sense amplifier drive line.
摘要翻译：电源线平行于包括在每个子阵列一侧的多个读出放大器的读出放大器串列布置。电源线通过多个驱动晶体管和读出放大器驱动线路连接到包括在读出放大器列中的读出放大器。

44. 发明授权

US5014241A Dynamic semiconductor memory device having reduced soft error rate 失效
标题翻译：具有降低的软错误率的动态半导体存储器件
公开(公告)号：US5014241A
公开(公告)日：1991-05-07
申请号：US337219
申请日：1989-04-12
申请人： Mikio Asakura , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Mikio Asakura , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/14 , G11C7/18 , G11C11/4096 , G11C11/4097 , G11C11/4099 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C11/4096 , G11C11/4097 , G11C11/4099 , G11C5/063 , G11C7/14 , G11C7/18
摘要： Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.
摘要翻译：读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。存储在存储单元中的信息被读出到两个位线之间的另一位线上。

45. 发明授权

US06414883B2 Semiconductor memory device 失效
公开(公告)号：US06414883B2
公开(公告)日：2002-07-02
申请号：US09860795
申请日：2001-05-21
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

46. 发明授权

US06404691B1 Semiconductor memory device for simple cache system 失效
标题翻译：半导体存储器件，用于简单缓存系统
公开(公告)号：US06404691B1
公开(公告)日：2002-06-11
申请号：US08472770
申请日：1995-06-07
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译：一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。在缓存命中时，数据被访问到SRAM存储单元阵列。在缓存未命中时，数据被存取到DRAM存储单元阵列。在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

47. 发明授权

US06301169B1 Semiconductor memory device with IO compression test mode 失效
标题翻译：半导体存储器件具有IO压缩测试模式
公开(公告)号：US06301169B1
公开(公告)日：2001-10-09
申请号：US09658011
申请日：2000-09-08
申请人： Shigeru Kikuda , Takeshi Hamamoto , Mikio Asakura
发明人： Shigeru Kikuda , Takeshi Hamamoto , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C29/40
摘要： In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data terminal. Thus, data having different logic levels can be written into adjacent memory cells even in an IO compression test mode.
摘要翻译：在由一列选择线选择的一组存储器单元中，至少1位的存储单元连接到内部数据线，该内部数据线与同一组中的另一个存储单元连接到的内部数据线不同。内部数据线对连接到数据终端。因此，即使在IO压缩测试模式下，也可以将具有不同逻辑电平的数据写入相邻存储单元。

48. 发明授权

US06301163B1 Semiconductor memory device and method of checking same for defect 有权
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06301163B1
公开(公告)日：2001-10-09
申请号：US09385582
申请日：1999-08-27
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C2900
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

49. 发明授权

US06207998B1 Semiconductor device with well of different conductivity types 有权
标题翻译：具有不同导电类型的半导体器件
公开(公告)号：US06207998B1
公开(公告)日：2001-03-27
申请号：US09329290
申请日：1999-06-10
申请人： Satoshi Kawasaki , Mikio Asakura , Kenji Tokami
发明人： Satoshi Kawasaki , Mikio Asakura , Kenji Tokami
IPC分类号： H01L2976
CPC分类号： H01L29/66181 , G11C11/4097 , H01L27/0629 , H01L27/10897
摘要： An MOS capacitor is provided in the proximity of the boundary between a P well and an N well formed of a bottom N well and an N well. Accordingly, the proximity of the boundary corresponding to the so-called dead space can be used effectively.
摘要翻译：在由P阱和N阱形成的N阱和N阱之间的边界附近提供MOS电容器。因此，可以有效地利用与所谓的死空间对应的边界的接近度。

50. 发明授权

US06197643B1 Method for making level converting circuit, internal potential generating circuit and internal potential generating unit 有权
标题翻译：制造电平转换电路，内部电位产生电路和内部电位产生单元的方法
公开(公告)号：US06197643B1
公开(公告)日：2001-03-06
申请号：US09338574
申请日：1999-06-23
申请人： Yuichiro Komiya , Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
发明人： Yuichiro Komiya , Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
IPC分类号： H01L218234
CPC分类号： G11C7/1078 , G11C5/145 , G11C5/146 , G11C5/147
摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.
摘要翻译：电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。第二电流切断电路包括连接到接地节点的两个NMOS晶体管。电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式