专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07120081B2 Multi-port memory device with stacked banks 有权
标题翻译：带堆叠银行的多端口存储设备
公开(公告)号：US07120081B2
公开(公告)日：2006-10-10
申请号：US10858659
申请日：2004-06-01
申请人： Seung-hoon Lee
发明人： Seung-hoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C5/02 , G11C7/1075
摘要： A multi-port memory device with stacked banks is provided. The multi-port memory device includes a number of ports, and a plurality of stacked banks, two or more of which share one data line sense amplifier. Each stacked bank includes a plurality of memory cells. Data line sense amplifiers are connected respectively between the stacked banks and read buffers to sense data read from memory cells of a selected bank among the stacked banks. The read buffers are connected respectively to the ports, store memory cell data output from the data line sense amplifiers, and output the stored data to the ports. Read data lines connect the data line sense amplifiers with the read buffers, respectively. Write buffers are connected respectively to the ports, and convert and store write data received in serial through the ports in a parallel form. Write data lines connect the data line drivers with the write buffers, respectively. Accordingly, since a plurality of stacked banks can be accessed independently and can perform reading and writing operations independently, a data throughput increases and a data reading speed and data writing speed are improved.
摘要翻译：提供了具有堆叠库的多端口存储器件。多端口存储器件包括多个端口和多个堆叠的组，其中两个或更多个共享一个数据线读出放大器。每个堆叠的存储体包括多个存储单元。数据线读出放大器分别连接在堆叠组和读缓冲器之间，以读取从堆叠组中选定存储体的存储单元读取的数据。读取缓冲器分别连接到端口，存储从数据线读出放大器输出的存储单元数据，并将存储的数据输出到端口。读数据线分别将数据线读出放大器与读缓冲器相连。写缓冲区分别连接到端口，并通过端口以并行形式转换和存储串行接收的写入数据。写数据线分别将数据线驱动器与写缓冲区相连。因此，由于可以独立地访问多个堆叠的组，并且可以独立地执行读取和写入操作，所以数据吞吐量增加，并且提高数据读取速度和数据写入速度。

42. 发明授权

US06473350B2 Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof 有权
标题翻译：具有具有改进的位线预充电时间的存储单元阵列结构的半导体存储器件及其方法
公开(公告)号：US06473350B2
公开(公告)日：2002-10-29
申请号：US09986181
申请日：2001-11-07
申请人： Seung-hoon Lee
发明人： Seung-hoon Lee
IPC分类号： G11C702
CPC分类号： G11C7/227 , G11C7/12 , G11C11/4094
摘要： A semiconductor memory device having a memory cell array structure and a precharging method, that improves bit line precharge time. The device has a common sense amplifier structure and includes memory cell blocks, first and second sense amplifiers and a dummy capacitor region. The first sense amplifier is arranged between and is shared by two adjacent memory cell blocks, to sense and detect data of memory cells. The second sense amplifier is connected to a memory cell block at an edge of the array structure, to sense and detect memory cell data. The dummy capacitor region includes capacitors between a dummy bit line and a complementary dummy bit line which are connected to the bit line and complementary bit line of the memory cell block at the edge of the array structure. The capacitors have a capacitance substantially equal to line capacitance of the bit line.
摘要翻译：具有提高位线预充电时间的具有存储单元阵列结构和预充电方法的半导体存储器件。该器件具有常读放大器结构，并且包括存储单元块，第一和第二读出放大器以及虚拟电容器区域。第一读出放大器布置在两个相邻存储器单元块之间并由两个相邻的存储单元块共享，以感测和检测存储器单元的数据。第二读出放大器连接到阵列结构边缘的存储器单元块，以感测和检测存储单元数据。虚拟电容器区域包括连接到阵列结构边缘处的存储单元块的位线和互补位线的虚拟位线和互补虚拟位线之间的电容器。电容器的电容基本上等于位线的线电容。

43. 发明申请

US20110037520A1 MULTISTAGE AMPLIFYING CIRCUIT 有权
标题翻译：多级放大电路
公开(公告)号：US20110037520A1
公开(公告)日：2011-02-17
申请号：US12841558
申请日：2010-07-22
申请人： MICHAEL CHOI , Ho-jin Park , Eun-seok Shin , Kyoung-jun Moon , Seung-hoon Lee , Kyung-hoon Lee , Young-ju Kim , Se-won Lee , Beom-soo Park
发明人： MICHAEL CHOI , Ho-jin Park , Eun-seok Shin , Kyoung-jun Moon , Seung-hoon Lee , Kyung-hoon Lee , Young-ju Kim , Se-won Lee , Beom-soo Park
IPC分类号： H03F3/68
CPC分类号： H03F3/45179 , H03F3/68 , H03F3/72
摘要： A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal.
摘要翻译：多级放大电路包括：第一放大电路，其响应于控制信号，对第一模拟电压输入进行采样或放大第一模拟电压与从第一模拟电压转换的第一数字电压之间的差。第二放大电路响应于控制信号对第二模拟电压输入进行采样或放大第二模拟电压与从第二模拟电压转换的第二数字电压之间的差。公共放大器接收第一放大电路和第二放大电路的输出电压，并且复位第一放大电路的输出电压，并通过使用第二放大电路确定输出电压，或者复位第二放大电路的输出电压，以及响应于控制信号，通过使用第一放大电路确定输出电压。

44. 发明申请

US20060273138A1 Soldering apparatus for printed circuit board, soldering method for printed circuit board and soldering cream printing unit for soldering printed circuit board 审中-公开
标题翻译：印刷电路板焊接设备，印刷电路板焊接方法和印刷电路板焊接焊膏印刷单元
公开(公告)号：US20060273138A1
公开(公告)日：2006-12-07
申请号：US11445203
申请日：2006-06-02
申请人： Seung-hoon Lee , Suk-young Kang , Il-jin Kim , Jun-chul Shin , Sang-kyoon Yoon
发明人： Seung-hoon Lee , Suk-young Kang , Il-jin Kim , Jun-chul Shin , Sang-kyoon Yoon
IPC分类号： A47J36/02
CPC分类号： H05K3/3415 , H05K3/3447 , H05K3/3484 , H05K2203/0126 , H05K2203/1476 , H05K2203/1563 , Y02P70/613
摘要： Provided is a soldering apparatus for a printed circuit board (PCB) for soldering the PCB and one or more electronic components populated on the PCB, the PCB having an upper side and a bottom side that is opposite the upper side, including a PCB INVERTING UNIT for rotatably supporting the PCB; a soldering cream PRINTING UNIT for printing on the lower side of the PCB a soldering cream substantially on a plurality of lead holes formed in the PCB in an inverted state, wherein in the inverted state a position of the PCB is inverted by the PCB INVERTING UNIT such that the lower side of the PCB faces in an upward direction; and a hardener for hardening the printed soldering cream while the one or more electronic components are inserted into the lead holes in a reverted state, wherein in the reverted state a position of the PCB is reverted by the PCB inverter such that the upper side of the PCB faces in a upward direction. Thus, provided is a soldering apparatus for a PCB, a soldering method for the PCB, and a soldering cream PRINTING UNIT for soldering on the PCB electronic components that are soldered on the PCB in high density and more reliability.
摘要翻译：本发明提供一种用于焊接印刷电路板的印刷电路板（PCB）和PCB上的一个或多个电子元件的焊接装置，PCB具有与上侧相对的上侧和底侧，包括PCB反相单元用于可旋转地支撑PCB; 一种焊膏印刷单元，用于在PCB的下侧印刷基本上在反相状态下形成在PCB中的多个引线孔上的焊膏，其中在倒置状态下，PCB的位置被PCB反相单元反转使得PCB的下侧面向上方向; 以及用于在所述一个或多个电子部件以回复状态插入所述引线孔中时硬化所述印刷焊膏的硬化剂，其中在所述还原状态下，所述PCB的位置由所述PCB逆变器回复，使得所述PCB逆变器的上侧 PCB面向上方。因此，提供了用于PCB的焊接装置，用于PCB的焊接方法以及用于以高密度和更可靠的方式焊接在PCB上焊接在PCB上的PCB电子部件的焊膏印刷单元。

45. 发明授权

US06985399B2 Main word line driver circuit receiving negative voltage in semiconductor memory device 失效
标题翻译：主字线驱动电路在半导体存储器件中接收负电压
公开(公告)号：US06985399B2
公开(公告)日：2006-01-10
申请号：US10748936
申请日：2003-12-30
申请人： Seung-hoon Lee
发明人： Seung-hoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C16/08
摘要： A main word line driver to which negative voltage is supplied in a semiconductor memory device is provided. The main word line driver circuit of a semiconductor memory device, the circuit which generates main word line signals enabling a plurality of main word lines, respectively, comprises a voltage supply unit which supplies a first voltage to a node and then supplies a second voltage higher than the first voltage; and a plurality of output units which receive the first voltage and second voltage supplied to the node and generate the respective main word line signals. In the circuit, the first voltage is a negative voltage and the second voltage is the ground voltage. Since the main word line driver circuit receives a negative voltage lower than a ground voltage and the ground voltage, the transition speed from a low level to a high level of a main word line signal does not decrease even during a low voltage operation of the main word line driver circuit.
摘要翻译：提供了在半导体存储器件中提供负电压的主字线驱动器。半导体存储器件的主字线驱动电路分别产生能够使多个主字线产生主字线信号的电路包括电压供应单元，该电压供应单元向节点提供第一电压，然后提供更高的第二电压比第一电压; 以及多个输出单元，其接收提供给所述节点的第一电压和第二电压并产生相应的主字线信号。在该电路中，第一电压为负电压，第二电压为接地电压。由于主字线驱动电路接收到低于接地电压和接地电压的负电压，所以即使在主电源电压低电压工作时，从主电源线信号的低电平到高电平的转换速度也不会降低字线驱动电路。

46. 发明申请

US20050218934A1 Output drivers having adjustable swing widths during test mode operation 有权
标题翻译：输出驱动器在测试模式操作期间具有可调整的摆幅宽度
公开(公告)号：US20050218934A1
公开(公告)日：2005-10-06
申请号：US11098818
申请日：2005-04-05
申请人： Seung-hoon Lee , Kee-won Kwon , Jung-hwan Choi
发明人： Seung-hoon Lee , Kee-won Kwon , Jung-hwan Choi
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H03K19/0175 , H03K19/0185 , H04L25/02
CPC分类号： H03K19/018585
摘要： An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.
摘要翻译：输出驱动器响应于输入信号和摆幅控制信号（TE）。输出驱动器被配置为当摆幅控制信号指定正常操作模式和第二摆幅宽度（例如，轨至轨）时，产生具有第一摆动宽度（例如，小于轨至轨）的输出信号，摇摆宽度控制信号指定测试操作模式时。

47. 发明授权

US06426902B1 Semiconductor memory device having redundancy circuit capable of improving redundancy efficiency 有权
标题翻译：具有能够提高冗余效率的冗余电路的半导体存储器件
公开(公告)号：US06426902B1
公开(公告)日：2002-07-30
申请号：US09657318
申请日：2000-09-07
申请人： Hi-choon Lee , Seung-hoon Lee , Hyung-dong Kim
发明人： Hi-choon Lee , Seung-hoon Lee , Hyung-dong Kim
IPC分类号： G11C700
CPC分类号： G11C29/787 , G11C29/808
摘要： A redundancy circuit is used to repair a normal column containing a defective normal memory cell. The redundancy circuit comprises a redundancy column containing redundancy memory cells and a plurality of programmable decoders. When any one of the plurality of programmable decoders enters a repair mode, a column pre-decoder for selecting a column containing a normal memory cell is disabled. Each of the programmable decoders can be configured to replace a column containing a defective normal memory cell in a single memory bank or a single memory bank group with a redundancy column. Since a defective column is replaced with a redundancy column in individual banks or bank groups, redundancy efficiency is greatly improved by allowing multiple normal columns containing defective cells to be replaced using a single redundancy column.
摘要翻译：冗余电路用于修复包含有缺陷的正常存储器单元的正常列。冗余电路包括冗余列，其包含冗余存储单元和多个可编程解码器。当多个可编程解码器中的任何一个进入修复模式时，用于选择包含正常存储器单元的列的列预解码器被禁用。每个可编程解码器都可以被配置为用冗余列替换包含单个存储体或单个存储体组中的有缺陷的正常存储单元的列。由于缺陷列被替换为单独存储体或存储体组中的冗余列，所以通过允许使用单个冗余列替换包含有缺陷单元的多个正常列，可大大提高冗余效率。

48. 发明授权

US06329863B1 Input circuit having a fuse therein and semiconductor device having the same 失效
标题翻译：具有熔断器的输入电路和具有其的半导体器件
公开(公告)号：US06329863B1
公开(公告)日：2001-12-11
申请号：US09477235
申请日：2000-01-04
申请人： Seung-hoon Lee , Tae-seong Jang
发明人： Seung-hoon Lee , Tae-seong Jang
IPC分类号： H03K508
CPC分类号： H01L23/50 , H01L23/5256 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an input circuit well-suited for use in a stacked-chip configuration, results in a reduction in input capacitance, and an overall improvement in transmission speed. The semiconductor device includes at least two bonding pads which receive external electrical input signals from a shared common external pin, and at least two internal circuits, each electrically coupled to a corresponding bonding pad by a signal transmission line. The semiconductor device further includes at least two protective elements, each electrically coupled to a corresponding signal transmission line, each for protecting the internal circuits from excessive electrical transmission characteristics in the input signal. At least two fuses are electrically coupled in series between the corresponding protective element and signal transmission line. The fuses are each capable of being opened to electrically insulate the protective elements from the bonding pads and the internal circuits. By keeping only one fuse active, and opening the rest, the overall system capacitance, as viewed by the common external pin, is greatly reduced.
摘要翻译：具有非常适合用于堆叠芯片配置的输入电路的半导体器件导致输入电容的降低和传输速度的总体改善。半导体器件包括至少两个接合焊盘，其接收来自共用公共外部引脚的外部电输入信号，以及至少两个内部电路，每个内部电路通过信号传输线电耦合到对应的焊盘。半导体器件还包括至少两个保护元件，每个保护元件电耦合到对应的信号传输线，每个保护元件用于保护内部电路免于输入信号中的过大的电传输特性。至少两个保险丝串联在相应的保护元件和信号传输线之间。保险丝均能够被打开以将保护元件与接合焊盘和内部电路电绝缘。通过保持只有一个保险丝激活，并打开其余的，由公共外部引脚所看到的整个系统电容大大减少。

49. 发明申请

US20120019544A1 IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：图像形成装置及其控制方法
公开(公告)号：US20120019544A1
公开(公告)日：2012-01-26
申请号：US13015686
申请日：2011-01-28
申请人： Young-jun Jang , Seung-hoon Lee
发明人： Young-jun Jang , Seung-hoon Lee
IPC分类号： G09G5/39
CPC分类号： G06F12/0804 , G11B2020/10759 , H04N21/4435 , H04N21/4436
摘要： An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory.
摘要翻译：提供一种包括主存储器的图像处理装置; 存储数据的至少一个子存储器，临时存储数据的高速缓冲存储器，以及控制是否相对于所述至少一个子存储器中的每一个有选择地将数据临时存储在高速缓冲存储器中的控制器。

50. 发明授权

US06873143B2 On-chip reference current and voltage generating circuits 有权
标题翻译：片内参考电流和电压发生电路
公开(公告)号：US06873143B2
公开(公告)日：2005-03-29
申请号：US10368398
申请日：2003-02-20
申请人： Kyoung-ho Moon , Seung-hoon Lee , Jong-bum Park , Hee-seuk Yang
发明人： Kyoung-ho Moon , Seung-hoon Lee , Jong-bum Park , Hee-seuk Yang
IPC分类号： G05F3/08 , G05F3/24 , H01L23/34
CPC分类号： G05F3/247 , G05F3/245 , H01L2924/0002 , Y10S323/907 , H01L2924/00
摘要： Provided is an on-chip reference current generating circuit for generating a reference voltage that can be digitally calibrated and is substantially not affected by changes in temperature and/or supply voltage. The on-chip reference current generating circuit includes a summing circuit for receiving a first current having a negative temperature coefficient and a second current having a positive temperature coefficient, and outputting a third current based upon, is a sum of, the first and second currents; and a digital calibration circuit for calibrating the third current to be the reference current in response to a digital control signal. Using the on-chip reference current generating circuit, it is possible to precisely and digitally calibrate an offset between currents due to a change in temperature and/or supply voltage.
摘要翻译：提供了片上参考电流产生电路，用于产生可被数字校准的基本电压，并且基本上不受温度和/或电源电压的变化的影响。片上参考电流产生电路包括一个加法电路，用于接收具有负温度系数的第一电流和具有正温度系数的第二电流，并且基于第一和第二电流的和来输出第三电流 ; 以及用于响应于数字控制信号校准作为参考电流的第三电流的数字校准电路。使用片上参考电流产生电路，可以由于温度和/或电源电压的变化而精确地和数字地校准电流之间的偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式