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41. 发明授权

US07167968B2 Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data 有权
标题翻译：用于打包十进制数据的存储预对齐和EBCDIC，ASCII和unicode基本拉丁转换
公开(公告)号：US07167968B2
公开(公告)日：2007-01-23
申请号：US10834637
申请日：2004-04-29
申请人： Fadi Y. Busaba , Steven R. Carlough , Mark A. Check , Christopher A. Krygowski , John G. Rell, Jr. , Frank Tanzi
发明人： Fadi Y. Busaba , Steven R. Carlough , Mark A. Check , Christopher A. Krygowski , John G. Rell, Jr. , Frank Tanzi
IPC分类号： G06F12/06
CPC分类号： G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F12/0886
摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.
摘要翻译：在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

42. 发明授权

US07167889B2 Decimal multiplication for superscaler processors 失效
标题翻译：超标量处理器的十进制乘法
公开(公告)号：US07167889B2
公开(公告)日：2007-01-23
申请号：US10436392
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
IPC分类号： G06F7/523
CPC分类号： G06F9/3001 , G06F7/496
摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.
摘要翻译：一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

43. 发明授权

US09335993B2 Convert from zoned format to decimal floating point format 有权
公开(公告)号：US09335993B2
公开(公告)日：2016-05-10
申请号：US13339791
申请日：2011-12-29
申请人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, Jr. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
发明人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, Jr. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F7/483 , G06F9/3001 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/3016
摘要： Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

44. 发明授权

US09152518B2 In situ processor re-characterization 有权
标题翻译：原位处理器重新表征
公开(公告)号：US09152518B2
公开(公告)日：2015-10-06
申请号：US13353544
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/24 , G06F1/26 , G06F1/32 , G06F1/20
CPC分类号： G06F11/24 , G06F1/206 , G06F1/32 , G06F1/324
摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.
摘要翻译：提供了重新表征处理，其调整处理器的一个或多个操作参数以改善处理器的健康状况（例如，减少错误）。参数包括电压和/或时钟频率，例如。处理器可以是对其执行重新表征处理的非活动或活动处理器。在一个实例中，它由硬件控制器实时执行。

45. 发明授权

US08954797B2 Reconfigurable recovery modes in high availability processors 有权
标题翻译：高可用性处理器中可重构的恢复模式
公开(公告)号：US08954797B2
公开(公告)日：2015-02-10
申请号：US13447554
申请日：2012-04-16
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/1446 , G06F1/3287 , G06F11/0772 , G06F11/0781 , G06F11/0793 , G06F11/1407 , G06F11/1425 , G06F11/1428 , Y02D10/171
摘要： A computer program product for performing error recovery is configured to perform a method that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.
摘要翻译：用于执行错误恢复的计算机程序产品被配置为执行包括由处理器创建恢复检查点的方法。基于创建软件恢复检查点，处理器被动态切换到不可恢复的处理操作模式。不可恢复的处理操作模式是硬件错误恢复资源的子集被掉电或重新用于指令处理的模式。在不可恢复的处理操作模式下，确定需要新的软件恢复检查点。基于确定需要新的软件恢复检查点，处理器被动态切换成可恢复的处理操作模式。可恢复处理操作模式是硬件错误恢复资源（包括该子集中的至少一个硬件错误恢复资源）用于硬件错误恢复操作的模式。

46. 发明授权

US08892958B2 Dynamic hardware trace supporting multiphase operations 有权
标题翻译：动态硬件跟踪支持多相操作
公开(公告)号：US08892958B2
公开(公告)日：2014-11-18
申请号：US13525054
申请日：2012-06-15
申请人： Steven R. Carlough , Juergen Haess , Michael K. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Juergen Haess , Michael K. Kroener , Silvia M. Mueller
IPC分类号： G06F11/00
CPC分类号： G06F11/3476 , G06F11/34 , G06F11/348 , G06F11/3636
摘要： In a data processing system a plurality of signals associated with an operation are received during execution of the operation. In response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selects and outputs as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selects and outputs as the trace signal a second signal of the plurality of signals.
摘要翻译：在数据处理系统中，在执行操作期间接收与操作相关联的多个信号。响应于操作是多相操作的指示，在执行操作期间，选择逻辑在多相操作的第一阶段期间，选择并输出多个信号的第一信号作为跟踪信号，并且在多相操作的第二相，选择并输出多个信号的第二信号作为迹线信号。

47. 发明申请

US20130275801A1 RECONFIGURABLE RECOVERY MODES IN HIGH AVAILABILITY PROCESSORS 有权
标题翻译：高可用性处理器中的可重构恢复模式
公开(公告)号：US20130275801A1
公开(公告)日：2013-10-17
申请号：US13447554
申请日：2012-04-16
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/14
CPC分类号： G06F11/1446 , G06F1/3287 , G06F11/0772 , G06F11/0781 , G06F11/0793 , G06F11/1407 , G06F11/1425 , G06F11/1428 , Y02D10/171
摘要： A computer program product for performing error recovery is configured to perform a method that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.
摘要翻译：用于执行错误恢复的计算机程序产品被配置为执行包括由处理器创建恢复检查点的方法。基于创建软件恢复检查点，处理器被动态切换到不可恢复的处理操作模式。不可恢复的处理操作模式是硬件错误恢复资源的子集被掉电或重新用于指令处理的模式。在不可恢复的处理操作模式下，确定需要新的软件恢复检查点。基于确定需要新的软件恢复检查点，处理器被动态切换成可恢复的处理操作模式。可恢复处理操作模式是硬件错误恢复资源（包括该子集中的至少一个硬件错误恢复资源）用于硬件错误恢复操作的模式。

48. 发明申请

US20130198492A1 MAJOR BRANCH INSTRUCTIONS 有权
公开(公告)号：US20130198492A1
公开(公告)日：2013-08-01
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

49. 发明申请

US20130198491A1 MAJOR BRANCH INSTRUCTIONS WITH TRANSACTIONAL MEMORY 有权
公开(公告)号：US20130198491A1
公开(公告)日：2013-08-01
申请号：US13362513
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467 , G06F9/528
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

50. 发明授权

US08229993B2 Method for performing decimal division 有权
标题翻译：执行小数除法的方法
公开(公告)号：US08229993B2
公开(公告)日：2012-07-24
申请号：US12358885
申请日：2009-01-23
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/496
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.
摘要翻译：一种用于执行小数除法的方法，包括将输入寄存器中的缩放除数和缩放的除数接收。缩放除数的倍数的子集存储在多个多个寄存器中。商数是根据缩放除数和缩放除数计算的。每个商数由流水线机构在三个时钟周期内计算。计算包括选择新的商数，并计算新的余数。计算新余数的输入包括来自一个或多个多个寄存器的数据。

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