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41. 发明授权

US5307464A Microprocessor and method for setting up its peripheral functions 失效
标题翻译：微处理器和设置其外设功能的方法
公开(公告)号：US5307464A
公开(公告)日：1994-04-26
申请号：US621641
申请日：1990-12-03
申请人： Yasushi Akao , Shiro Baba , Yoshiyuki Miwa , Terumi Sawase , Yuji Sato , Shigeki Masumura
发明人： Yasushi Akao , Shiro Baba , Yoshiyuki Miwa , Terumi Sawase , Yuji Sato , Shigeki Masumura
IPC分类号： G06F13/12 , G06F15/78 , G06F13/00
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.
摘要翻译：单片微处理器1包括用于软件实现微处理器1的外围功能的CPU 2和子处理器5.子处理器5包括电可写内部存储设备微程序存储单元13和用于存储软件的顺控控制存储单元62 。通过将软件写入存储器单元13和62来定义和/或修改外围功能。因此，定义和/或修改外围功能所花费的时间是编程存储器单元13和62所花费的时间。子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14.另外，微程序存储单元13向执行单元16提供微指令。顺序控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。顺序控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11的选择顺序的信息。每次读序列控制存储器单元62选择地址寄存器MAR0至MAR11中的一个。存储在选择的地址寄存器中的微地址然后被提供给微程序存储单元13。

42. 发明授权

US06889240B2 Data processing device having a central processing unit and digital signal processing unit 失效
标题翻译：具有中央处理单元和数字信号处理单元的数据处理装置
公开(公告)号：US06889240B2
公开(公告)日：2005-05-03
申请号：US10694771
申请日：2003-10-29
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

43. 发明授权

US5884092A System for maintaining fixed-point data alignment within a combination CPU and DSP system 失效
标题翻译：用于在CPU和DSP系统组合中保持定点数据对齐的系统
公开(公告)号：US5884092A
公开(公告)日：1999-03-16
申请号：US725481
申请日：1996-10-04
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction.This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理器被安装在同一个发明中，防止了数量的增加由计算器处理的不同类型的数据引起的处理步骤，从而提高数字信号处理的效率。数字信号处理单元是处理定点数据的计算单元，并且与常规整数计算指令分开提供调用执行定点数据计算的指令。当在数字信号处理单元和存储器或外部电路之间的数据传送中，位长度比传送计算精度更短的数据时，计算单元具有向数据信号处理单元和存储器或外部电路的高阶侧输入和输出数据的功能，存储数据的寄存器和固定点数据传送指令与传统的整数数据传送指令分开提供。本发明可以消除当整数数据处理单元执行数字信号处理时所需的附加校正处理。

44. 发明授权

US5511211A Method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions 失效
标题翻译：用于灵活地开发数据处理系统的方法，包括在功能检查之后重写非易失性存储器元件中的指令，指示所需功能的失败
公开(公告)号：US5511211A
公开(公告)日：1996-04-23
申请号：US102156
申请日：1993-08-04
申请人： Yasushi Akao , Shiro Baba , Terumi Sawase , Yoshimune Hagiwara
发明人： Yasushi Akao , Shiro Baba , Terumi Sawase , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F9/445 , G06F15/78 , G06F9/312 , G06F13/40 , G06F15/20
CPC分类号： G06F8/60 , G06F15/7814 , G06F9/24
摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.
摘要翻译：在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据将系统的所需规格和功能写入逻辑功能块。由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。

45. 发明授权

US5410718A Single-chip microcomputer having a memory including a one-bit memory element which has 3 inputs and a selector for selecting one of the inputs 失效
标题翻译：具有包括具有3个输入的一位存储元件和用于选择其中一个输入的选择器的存储器的单片微计算机
公开(公告)号：US5410718A
公开(公告)日：1995-04-25
申请号：US795985
申请日：1991-11-22
申请人： Shigeki Masumura , Tatsuya Aizawa , Kazuo Naito , Yoshiyuki Miwa , Hideo Nakamura , Terumi Sawase , Yasushi Akao
发明人： Shigeki Masumura , Tatsuya Aizawa , Kazuo Naito , Yoshiyuki Miwa , Hideo Nakamura , Terumi Sawase , Yasushi Akao
IPC分类号： G06F13/38 , G06F15/78 , G11C7/00 , G06F12/00
CPC分类号： G06F15/7867 , G06F15/7814
摘要： A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities.
摘要翻译：单片微计算机包括微处理器，用于执行外围功能的子处理器，用于控制来自外部设备的输入/输出操作的外部端口和用于从内部输入多个数据的多功能逻辑存储器至少一个微处理器，子处理器和外部端口，并且根据预定的优先级从多个数据中选择写入数据。

46. 发明授权

US5361374A Integrated data processor having mode control register for controlling operation mode of serial communication unit 失效
标题翻译：具有用于控制串行通信单元的操作模式的模式控制寄存器的集成数据处理器
公开(公告)号：US5361374A
公开(公告)日：1994-11-01
申请号：US49347
申请日：1993-04-21
申请人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
发明人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.
摘要翻译：用于将从串行输入电路提供的数据提供给内部总线的接收单元和用于将从内部总线提供的数据提供给串行输出电路的传输单元在HDLC程序，BI-SYNC程序中保持至少两种控制程序以及作为数据发送/接收的控制过程的起始 - 停止同步过程，并且可以基于处理器的命令交替地选择由这些单元保持的控制过程。

47. 发明授权

US4989208A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US4989208A
公开(公告)日：1991-01-29
申请号：US39695
申请日：1987-04-20
申请人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
发明人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
IPC分类号： G06F11/22 , G06F11/267 , G06F15/78
CPC分类号： G06F11/2236 , G06F15/7814
摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.
摘要翻译：在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块在一个半导体衬底上。地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是直接读取外部设备。因此，提高了测试效率。

48. 发明授权

US4881167A Data memory system 失效
标题翻译：数据存储系统
公开(公告)号：US4881167A
公开(公告)日：1989-11-14
申请号：US318439
申请日：1989-03-02
申请人： Hisao Sasaki , Matsuaki Terada , Susumu Matsui , Kenji Kawakita , Jiro Kashio , Shiro Baba , Yasushi Akao , Toshio Okochi
发明人： Hisao Sasaki , Matsuaki Terada , Susumu Matsui , Kenji Kawakita , Jiro Kashio , Shiro Baba , Yasushi Akao , Toshio Okochi
IPC分类号： G06F3/06 , G06F5/06 , G06F12/02 , G06F12/04 , G06F12/06
CPC分类号： H04L49/901 , G06F12/06 , G06F5/06 , H04L49/90 , H04L49/9021 , G06F2205/064
摘要： A data memory system includes a plurality of buffer regions each having a constant size so that serial data may be stored by linking the buffer regions. A descripter provided to correspond to each of the buffer regions includes memory region addressing information indicating the head address of the corresponding buffer region, data delimiting information indicating whether or not the data to be stored is terminated in the corresponding buffer region, and chain information indicating the head address of a next subsequent descripter.
摘要翻译：数据存储系统包括多个缓冲区，每个缓冲区具有恒定的大小，从而通过链接缓冲区可以存储串行数据。提供用于对应于每个缓冲区的描述符包括指示相应缓冲区的头地址的存储器区域寻址信息，指示要存储的数据是否终止在相应的缓冲区中的数据定界信息，以及指示下一个下一个描述符的头地址。

49. 发明授权

US06367050B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06367050B1
公开(公告)日：2002-04-02
申请号：US09399229
申请日：1999-09-20
申请人： Yasushi Akao , Kenichi Kuroda
发明人： Yasushi Akao , Kenichi Kuroda
IPC分类号： G06F1750
CPC分类号： G06F15/7814
摘要： A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.
摘要翻译：一种半导体集成电路装置，包括具有非易失性存储器电路的单片微计算机，并且与处理器的周期时间保持高速执行写入和读取操作。存储器电路的一部分被设置为用于容纳数据处理程序的只读区域，并且其余的存储器用于向其写入和读取数据。由于不需要优化存储器电路中的ROM和RAM部件的分配，所以单芯片微芯片易于以高生产率进行设计和制造。根据需要建立程序存储区域，用户比以前更容易使用单片机。

50. 发明授权

US5426744A Single chip microprocessor for satisfying requirement specification of users 失效
标题翻译：单芯片微处理器，用于满足用户的要求规格
公开(公告)号：US5426744A
公开(公告)日：1995-06-20
申请号：US203761
申请日：1994-03-01
申请人： Terumi Sawase , Yoshimune Hagiwara , Hideo Nakamura , Hiroyuki Hatori , Shirou Baba , Yasushi Akao
发明人： Terumi Sawase , Yoshimune Hagiwara , Hideo Nakamura , Hiroyuki Hatori , Shirou Baba , Yasushi Akao
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78 , G06F9/26
CPC分类号： G06F9/3879 , G06F11/2236 , G06F15/7814 , G06F15/7867 , G06F9/24 , G06F9/3897
摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.
摘要翻译：本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。可以通过任意形成的逻辑功能来满足各种用户的需求规格。

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