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41. 发明申请

US20110116184A1 MAGNETIC HEAD HAVING A MULTILAYER MAGNETIC FILM AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：具有多层磁性膜的磁头及其制造方法
公开(公告)号：US20110116184A1
公开(公告)日：2011-05-19
申请号：US12941953
申请日：2010-11-08
申请人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
发明人： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
IPC分类号： G11B5/127 , G11B21/02 , G11B5/02
CPC分类号： G11B5/398 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/02 , G11B5/1278 , G11B5/3146 , G11B5/3163 , G11B5/3906 , G11B2005/0002 , G11B2005/0024 , H01F10/3254 , H01F10/3263 , H01F10/329
摘要： According to one embodiment, a method for producing a magnetic head includes depositing a first film above a substrate, etching a pattern into the first film, depositing a second film on the etched portion of the first film, and depositing a third film above the first and second film to form a multilayer magnetic film, wherein the second film is embedded between the first and third film in a portion of the first film that is removed. In another embodiment, a differential magnetic read head includes a magnetic multilayer film comprising a stack of a first magnetic sensor film and a second magnetic sensor film which are not magnetically connected and a hard magnetic film provided on both sides in a track width direction of the magnetic multilayer film for controlling a magnetic domain of the magnetic multilayer film. The hard magnetic film is a laminated structure as described above.
摘要翻译：根据一个实施例，一种用于制造磁头的方法包括在基板上沉积第一膜，将图案蚀刻到第一膜中，在第一膜的蚀刻部分上沉积第二膜，以及在第一膜上沉积第三膜和第二膜以形成多层磁性膜，其中第二膜在被去除的第一膜的一部分中嵌入第一和第三膜之间。在另一个实施例中，差分磁读头包括磁性多层膜，该磁性多层膜包括不磁性连接的第一磁性传感器膜和第二磁性传感器膜的叠层，以及设置在第二磁性传感器膜的轨道宽度方向上的两侧的硬磁性膜用于控制磁性多层膜的磁畴的磁性多层膜。硬磁性膜是如上所述的层叠结构。

42. 发明申请

US20100203697A1 INTEGRATED SEMICONDUCTOR NONVOLATILE STORAGE DEVICE 有权
标题翻译：集成半导体非易失存储器件
公开(公告)号：US20100203697A1
公开(公告)日：2010-08-12
申请号：US12763402
申请日：2010-04-20
申请人： Digh HISAMOTO , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
发明人： Digh HISAMOTO , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0425 , H01L21/28282 , H01L27/11568 , H01L29/792
摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
摘要翻译：本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。为了克服这个问题，本发明的集成半导体非易失性存储装置被配置成使得具有不同存储器栅极长度的存储单元集成在同一芯片上。这允许以高速读取设备并重新编程增加的次数。

43. 发明申请

US20100105199A1 NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE 有权
标题翻译：非挥发性半导体器件及其制造嵌入式非易失性半导体存储器件的方法
公开(公告)号：US20100105199A1
公开(公告)日：2010-04-29
申请号：US12652517
申请日：2010-01-05
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
IPC分类号： H01L21/28
CPC分类号： H01L27/115 , G11C16/0425 , H01L27/11568 , H01L29/42344
摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
摘要翻译：提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的不同而引入的注入离子的问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和缩放MOS晶体管。形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于在逻辑区域的栅电极。栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

44. 发明申请

US20090152619A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20090152619A1
公开(公告)日：2009-06-18
申请号：US12368538
申请日：2009-02-10
申请人： DIGH HISAMOTO , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
发明人： DIGH HISAMOTO , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.
摘要翻译：提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

45. 发明授权

US07529126B2 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US07529126B2
公开(公告)日：2009-05-05
申请号：US11472993
申请日：2006-06-23
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0433
摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.
摘要翻译：这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1iA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

46. 发明申请

US20090014775A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20090014775A1
公开(公告)日：2009-01-15
申请号：US12233670
申请日：2008-09-19
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： H01L29/00
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

47. 发明申请

US20070210371A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS FABRICATION METHOD 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070210371A1
公开(公告)日：2007-09-13
申请号：US11653832
申请日：2007-01-17
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.
摘要翻译：存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

48. 发明申请

US20070183206A1 Semiconductor nonvolatile memory device 失效
标题翻译：半导体非易失性存储器件
公开(公告)号：US20070183206A1
公开(公告)日：2007-08-09
申请号：US11727592
申请日：2007-03-27
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

49. 发明授权

US07199022B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07199022B2
公开(公告)日：2007-04-03
申请号：US10814627
申请日：2004-04-01
申请人： Kan Yasui , Toshiyuki Mine , Yasushi Goto , Natsuki Yokoyama
发明人： Kan Yasui , Toshiyuki Mine , Yasushi Goto , Natsuki Yokoyama
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , Y10S438/907
摘要： In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.
摘要翻译：为了实现根据本发明的隔离沟槽形成方法，其中可以容易地控制氮化硅膜衬垫的结构并且允许器件特征长度的减小和在隔离沟槽中发生的应力的减小，氮化硅膜衬垫首先沉积在形成在硅衬底上的沟槽的内壁上。用于填充沟槽内部的第一嵌入式绝缘体膜的上表面向下凹入以暴露氮化硅膜衬垫的上端部分。接下来，将氮化硅膜衬垫的露出部分转换成诸如氧化硅膜的非氮化硅型绝缘膜。然后将第二嵌入式绝缘膜沉积在第一嵌入式绝缘膜的上部上，然后将沉积的表面平坦化。

50. 发明授权

US07085157B2 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US07085157B2
公开(公告)日：2006-08-01
申请号：US10805365
申请日：2004-03-22
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0433
摘要： A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.
摘要翻译：一种用于通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入和降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1AA的恒定电流，并且通过约1μA的恒定电流放电位线以使存储器单元中的电流流动。

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