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    • 41. 发明授权
    • Semiconductor digital circuit, FIFO buffer circuit, and data transferring method
    • 半导体数字电路,FIFO缓冲电路和数据传输方法
    • US07821850B2
    • 2010-10-26
    • US12090207
    • 2006-10-13
    • Kazumasa Suzuki
    • Kazumasa Suzuki
    • G11C7/00G11C7/10
    • H03K19/0185
    • A FIFO buffer circuit is provided which, in data transmission between two circuit areas having different combinations of a power supply voltage and an operation clock frequency, can perform voltage level and clock rate conversion at the same place and time. In an input side area are a plurality of data entry registers, a write entry management circuit and a full signal generating circuit. In an output side area are a read entry management circuit, an empty signal generating circuit and an output selector. On the boundary between the input and output sides are entry management flag circuits that manage the presence or absence of effective data in the respective data entries; and voltage level converting circuits that convert voltage levels of the outputs of the data entry registers to the voltage levels of the output side. In this way, the clock rate replacements and voltage level conversions are performed.
    • 提供了一种FIFO缓冲电路,其在具有不同电源电压和操作时钟频率的组合的两个电路区域之间的数据传输中可以在相同的地点和时间执行电压电平和时钟速率转换。 在输入侧区域是多个数据输入寄存器,写入条目管理电路和全信号生成电路。 在输出侧区域是读入口管理电路,空信号发生电路和输出选择器。 在输入侧和输出侧之间的边界上是管理相应数据条目中有效数据的存在或不存在的入口管理标志电路; 以及将数据输入寄存器的输出的电压电平转换为输出侧的电压电平的电压电平转换电路。 以这种方式,执行时钟速率替换和电压电平转换。