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41. 发明授权

US08426281B2 Lateral metal oxide semiconductor drain extension design 有权
标题翻译：横向金属氧化物半导体漏极扩展设计
公开(公告)号：US08426281B2
公开(公告)日：2013-04-23
申请号：US12961885
申请日：2010-12-07
申请人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
发明人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.
摘要翻译：包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于源极和漏极区域。绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个绝缘条纹

42. 发明授权

US08253193B2 MOS transistor with gate trench adjacent to drain extension field insulation 有权
公开(公告)号：US08253193B2
公开(公告)日：2012-08-28
申请号：US13006566
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/66
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

43. 发明申请

US20120112277A1 INTEGRATED LATERAL HIGH VOLTAGE MOSFET 有权
标题翻译：集成式横向高压MOSFET
公开(公告)号：US20120112277A1
公开(公告)日：2012-05-10
申请号：US13284011
申请日：2011-10-28
申请人： Marie Denison , Sameer Pendharkar , Philip L. Hower
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/265 , H01L21/823814 , H01L27/0922 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
摘要翻译：一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

44. 发明授权

US07888196B2 Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权
标题翻译：包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离
公开(公告)号：US07888196B2
公开(公告)日：2011-02-15
申请号：US12345072
申请日：2008-12-29
申请人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
发明人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/76229 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness
摘要翻译：一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管，其中所述第一厚度<所述第二厚度。提供具有半导体表面的衬底。具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。在包括第二区域的半导体表面上形成硬掩模层。通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。然后完成第一和第二区域中的MOS晶体管的制造。

45. 发明申请

US20090294841A1 Formation of a MOSFET Using an Angled Implant 有权
标题翻译：使用倾斜植入物形成MOSFET
公开(公告)号：US20090294841A1
公开(公告)日：2009-12-03
申请号：US12509922
申请日：2009-07-27
申请人： Sameer Pendharkar , Binghua Hu
发明人： Sameer Pendharkar , Binghua Hu
IPC分类号： H01L29/78
CPC分类号： H01L29/66712 , H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/1083 , H01L29/1095 , H01L29/66681 , H01L29/7809 , H01L29/7816
摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.
摘要翻译：一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％身体区域。此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

46. 发明授权

US07514292B2 Individualized low parasitic power distribution lines deposited over active integrated circuits 有权
标题翻译：沉积在有源集成电路上的个性化的低寄生配电线路
公开(公告)号：US07514292B2
公开(公告)日：2009-04-07
申请号：US11539486
申请日：2006-10-06
申请人： Taylor R Efland , Milton L Buschbom , Sameer Pendharkar
发明人： Taylor R Efland , Milton L Buschbom , Sameer Pendharkar
IPC分类号： H01L21/00
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05187 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49175 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13055 , H01L2924/14 , H01L2924/15724 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/04953 , H01L2924/00 , H01L2924/00012 , H01L2224/48869
摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/· and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
摘要翻译：安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源线路下方的组件，以及引线框架的导体。此外，线路的薄层电阻小于1.5mOmega /。并且大多数线分别被图案化为通孔和导体之间的直线。

47. 发明授权

US07135759B2 Individualized low parasitic power distribution lines deposited over active integrated circuits 有权
标题翻译：沉积在有源集成电路上的个性化的低寄生配电线路
公开(公告)号：US07135759B2
公开(公告)日：2006-11-14
申请号：US10039663
申请日：2001-10-22
申请人： Taylor R. Efland , Milton L. Buschbom , Sameer Pendharkar
发明人： Taylor R. Efland , Milton L. Buschbom , Sameer Pendharkar
IPC分类号： H01L23/495
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05184 , H01L2224/05187 , H01L2224/05554 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49175 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/13055 , H01L2924/14 , H01L2924/15724 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/04953 , H01L2924/00 , H01L2924/00012 , H01L2224/48869
摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
摘要翻译：安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源线路下方的组件，以及引线框架的导体。此外，线路的薄层电阻小于1.5mOmega /□，并且大部分线路分别图案化为通孔和导体之间的直线。

48. 发明申请

US20060194401A1 Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process 有权
标题翻译：用于制造具有使用N型掺杂剂形成的取向特征和湿式氧化处理的半导体器件的方法
公开(公告)号：US20060194401A1
公开(公告)日：2006-08-31
申请号：US11068117
申请日：2005-02-28
申请人： Binghua Hu , Sameer Pendharkar , Bill Wofford , Joseph Ramirez
发明人： Binghua Hu , Sameer Pendharkar , Bill Wofford , Joseph Ramirez
IPC分类号： H01L21/331 , H01L21/76
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/2652 , H01L21/823493 , H01L21/8249 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.
摘要翻译：本发明提供一种具有对准特征的半导体器件的制造方法。除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。该方法可以进一步包括使用湿式氧化法，湿式氧化法和n型掺杂剂使注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分从而在植入区域附近留下对准特征。

49. 发明申请

US20060186467A1 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US20060186467A1
公开(公告)日：2006-08-24
申请号：US11063312
申请日：2005-02-21
申请人： Sameer Pendharkar , Jonathan Brodsky
发明人： Sameer Pendharkar , Jonathan Brodsky
IPC分类号： H01L29/76
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

50. 发明申请

US20060051933A1 Drain extended MOS transistor with improved breakdown robustness 有权
标题翻译：漏极扩展MOS晶体管具有更好的击穿稳定性
公开(公告)号：US20060051933A1
公开(公告)日：2006-03-09
申请号：US11198038
申请日：2005-08-05
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L21/76
CPC分类号： H01L29/0653 , H01L29/0615 , H01L29/0638 , H01L29/0692 , H01L29/42368 , H01L29/7835
摘要： A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.
摘要翻译：公开了具有改进的击穿特性鲁棒性的漏极延伸金属氧化物半导体晶体管（40）。场源氧化物隔离结构（29c）设置在源极区域（30）和漏极接触区域（32a，32b，32c）之间，以将晶体管的沟道区域断开成平行段。栅极电极（35）在多个沟道区域上延伸，并且下面的阱（26）以及晶体管的漂移区域（DFT）沿整个沟道宽度延伸。通道阻挡掺杂区域（33）位于场氧化物隔离结构（29c）的下面，并且在击穿期间为载体提供导电路径。因此避免了寄生双极导电和由于导电导致的损坏。

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