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41. 发明申请

US20080102622A1 Method of forming metal line in semiconductor device 审中-公开
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080102622A1
公开(公告)日：2008-05-01
申请号：US11647088
申请日：2006-12-27
申请人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
发明人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.
摘要翻译：一种在半导体器件中形成金属线的方法，包括以下步骤：在通过镶嵌工艺形成金属线时，通过使用非金属材料在虚拟区域上形成虚拟图案的半导体器件中形成金属线以防止由化学机械抛光（CMP）工艺中使用的浆料和清洗液在铝层上形成氧化物层，并进行均匀的抛光工艺，从而可以防止在金属层上的挖掘现象从被生成。

42. 发明申请

US20080081465A1 Method for Fabricating Semiconductor Device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20080081465A1
公开(公告)日：2008-04-03
申请号：US11747444
申请日：2007-05-11
申请人： Jung Geun Kim , Cheol-Mo Jeong , Whee-Won Cho , Seong-Hwan Myung
发明人： Jung Geun Kim , Cheol-Mo Jeong , Whee-Won Cho , Seong-Hwan Myung
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28273
摘要： A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.
摘要翻译：一种制造半导体器件的方法，其中可以防止在具有拉伸应力的蚀刻层上形成非晶碳膜而发生提升现象。根据本发明，由于可以减小蚀刻层或非晶碳膜上的压缩应力，或者在蚀刻层或非晶碳膜之间形成压缩应力膜，以防止发生升降现象，因此可以是其他图案形成以制造高度集成的半导体器件。

43. 发明授权

US07033907B2 Method for forming isolation layer of semiconductor device 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07033907B2
公开(公告)日：2006-04-25
申请号：US10878451
申请日：2004-06-28
申请人： Jung Geun Kim
发明人： Jung Geun Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/76229
摘要： A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench having a second size, which is larger than the first size of the first trench, in the peripheral circuit region; forming a sidewall oxide layer on surfaces of the first trench and the second trench; sequentially depositing a liner nitride layer and a liner oxide layer on a resultant substrate inclusive of the sidewall oxide layer; performing a plasma pre-heating process using O2+He with respect to the resultant substrate in an HDP CVD process chamber and selectively oxidizing a portion of the liner nitride layer remaining on a bottom of the second trench in the peripheral circuit region; continuously depositing an HDP oxide layer on the resultant substrate having been subjected to the plasma pre-heating process, thereby filling the trenches; and performing a chemical mechanical polishing process with respect to the HDP oxide layer.
摘要翻译：公开了一种用于形成半导体器件的隔离层的方法，其包括以下步骤：蚀刻具有单元区域和外围电路区域的硅衬底，在单元区域中形成具有第一尺寸的第一沟槽，并形成在外围电路区域中具有大于第一沟槽的第一尺寸的第二尺寸的第二沟槽; 在所述第一沟槽和所述第二沟槽的表面上形成侧壁氧化物层; 在包括侧壁氧化物层的所得衬底上依次沉积衬里氮化物层和衬垫氧化物层; 在HDP CVD处理室中使用O 2 H 2 He对所得衬底进行等离子体预热处理，并且选择性地氧化残留在第二沟槽的底部上的衬里氮化物层的一部分外围电路区域; 在经过等离子体预热处理的所得基板上连续沉积HDP氧化物层，从而填充沟槽; 对HDP氧化物层进行化学机械研磨处理。

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