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41. 发明申请

US20090010526A1 TUNGSTEN PLUG DEPOSITION QUALITY EVALUATION METHOD BY EBACE TECHNOLOGY 有权
标题翻译： EBACE技术的TUNGSTEN PLUG沉积质量评估方法
公开(公告)号：US20090010526A1
公开(公告)日：2009-01-08
申请号：US11622793
申请日：2007-01-12
申请人： Yehiel Gotkis , Sergey Lopatin , Mehran Nasser-Ghodsi
发明人： Yehiel Gotkis , Sergey Lopatin , Mehran Nasser-Ghodsi
IPC分类号： G06K9/00 , G01R31/26 , H01L23/58
CPC分类号： H01L22/12 , H01L22/34
摘要： A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.
摘要翻译：本发明的第一实施例涉及一种用于评估集成电路晶片上的结构质量的方法。在集成的或在测试晶片上形成的测试结构暴露于电子束和电子束激活的化学蚀刻。电子束活化的蚀刻气体或蒸气蚀刻测试结构，其在蚀刻后分析以确定测试结构的质量的度量。可以在统计过程控制中使用质量测量来调整用于在集成电路晶片上形成器件结构的参数。测试结构形成在具有两个或更多个管芯的集成电路晶片上。每个管芯具有一个或多个集成电路结构。测试结构形成在两个或更多相邻模具之间的划线上。每个测试结构可以在尺寸和/或组成上与一个或多个集成电路结构相对应。

42. 发明申请

US20080132082A1 PRECISION PRINTING ELECTROPLATING THROUGH PLATING MASK ON A SOLAR CELL SUBSTRATE 失效
标题翻译：精密印刷通过太阳能电池基板上的电镀掩模进行电镀
公开(公告)号：US20080132082A1
公开(公告)日：2008-06-05
申请号：US11566205
申请日：2006-12-01
申请人： Sergey Lopatin , John O. Dukovic , David Eaglesham , Nicolay Y. Kovarsky , Robert Bachrach , John Busch , Charles Gay
发明人： Sergey Lopatin , John O. Dukovic , David Eaglesham , Nicolay Y. Kovarsky , Robert Bachrach , John Busch , Charles Gay
IPC分类号： H01L21/469 , B05C13/02
CPC分类号： H01L31/022425 , H01L31/02008 , Y02E10/50
摘要： Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper. Embodiments of the invention may provide an apparatus and method of forming a solar cell device that utilizes a reusable masking device during one or more electrochemical deposition steps.
摘要翻译：本发明的实施例考虑使用新型电镀设备和方法形成低成本太阳能电池，以形成具有使用电化学电镀工艺形成的金属线的金属接触结构。本文描述的装置和方法不需要执行经常昂贵的处理步骤来执行掩模准备和形成步骤，例如丝网印刷，光刻步骤和喷墨印刷步骤，以形成接触结构。在太阳能电池器件中形成的互连的电阻极大地影响太阳能电池的效率。因此，希望形成具有可靠和成本有效的低电阻连接的太阳能电池装置。因此，本文描述的本发明的一个或多个实施例适用于使用包含普通金属（例如铜）的电化学电镀工艺形成低成本且可靠的互连层。本发明的实施例可以提供一种形成在一个或多个电化学沉积步骤期间利用可重复使用的掩模装置的太阳能电池装置的装置和方法。

43. 发明申请

US20070158303A1 STRUCTURAL MODIFICATION USING ELECTRON BEAM ACTIVATED CHEMICAL ETCH 失效
标题翻译：使用电子束激活化学蚀刻的结构改性
公开(公告)号：US20070158303A1
公开(公告)日：2007-07-12
申请号：US11622625
申请日：2007-01-12
申请人： MEHRAN NASSER-GHODSI , Garrett Pickard , Rudy Garcia , Ming Yu , Kenneth Krzeczowski , Matthew Lent , Sergey Lopatin , Chris Huang , Niles MacDonald
发明人： MEHRAN NASSER-GHODSI , Garrett Pickard , Rudy Garcia , Ming Yu , Kenneth Krzeczowski , Matthew Lent , Sergey Lopatin , Chris Huang , Niles MacDonald
IPC分类号： C23F1/00 , A61N5/00 , B44C1/22 , G21G5/00
CPC分类号： C23F4/00 , G02B5/1857 , H01J2237/31744 , H01L21/3065 , H01L21/32136 , H01L29/66795
摘要： Structural modification using electron beam activated chemical etch (EBACE) is disclosed. A target or portion thereof may be exposed to a gas composition of a type that etches the target when the gas composition and/or target are exposed to an electron beam. By directing an electron beam toward the target in the vicinity of the gas composition, an interaction between the electron beam and the gas composition etches a portion of the target exposed to both the gas composition and the electron beam. Structural modifications of the target may be conducted by means of etching due to interaction between the electron beam and gas composition.
摘要翻译：公开了使用电子束活化化学蚀刻（EBACE）的结构修饰。当气体组合物和/或靶暴露于电子束时，靶或其部分可暴露于蚀刻靶的类型的气体组合物。通过在气体组合物附近引导电子束朝向靶，电子束和气体组成之间的相互作用会蚀刻暴露于气体组成和电子束两者的靶的一部分。由于电子束和气体组成之间的相互作用，靶的结构修饰可以通过蚀刻进行。

44. 发明授权

US06936925B1 Semiconductor device having copper lines with reduced electromigration using an electroplated interim copper-zinc alloy film on a copper surface 失效
标题翻译：具有在铜表面上使用电镀的中间铜 - 锌合金膜的具有减少的电迁移的铜线的半导体器件
公开(公告)号：US06936925B1
公开(公告)日：2005-08-30
申请号：US10626371
申请日：2003-07-23
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： C25D3/58 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： The present invention relates to the semiconductor device fabrication industry. More particularly a semiconductor device, having an interim reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35). The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译：本发明涉及半导体器件制造业。更具体地说，一种半导体器件，具有通过使用电镀设备电镀Cu，Cu表面（20）上电镀在布置在通孔（6）上的铜箔表面（20）上的临时还原氧Cu-Zn合金薄膜（30））在一种独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）。通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。

45. 发明申请

US20050124158A1 Silver under-layers for electroless cobalt alloys 有权
标题翻译：无电钴合金的银层
公开(公告)号：US20050124158A1
公开(公告)日：2005-06-09
申请号：US10967101
申请日：2004-10-15
申请人： Sergey Lopatin , Arulkumar Shanmugasundrum , Yosef Shacham-Diamand
发明人： Sergey Lopatin , Arulkumar Shanmugasundrum , Yosef Shacham-Diamand
IPC分类号： C23C18/50 , H01L21/288 , H01L21/44 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , C23C18/50 , C23C28/021 , C23C28/023 , H01L21/288 , H01L21/76849 , H01L21/76852 , H01L21/76874
摘要： In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution to form a zinc layer on the copper layer. The method further includes exposing the substrate surface to a silver solution to form a silver layer on the zinc layer, and depositing the capping layer on the silver layer by an electroless deposition process. A second silver layer may be formed on the capping layer, if desired. In another embodiment, a composition of a deposition solution to deposit a cobalt tungsten alloy is disclosed. The deposition solution includes CaWO4, a cobalt source in a range from about 50 mM to about 500 mM, a complexing agent in a range from about 100 mM to about 700 mM and a buffering agent in a range from about 50 mM to about 500 mM.
摘要翻译：在一个实施例中，提供了一种用于在包含铜层的衬底表面上沉积覆盖层的方法，其包括将衬底表面暴露于锌溶液以在铜层上形成锌层。该方法还包括将衬底表面暴露于银溶液以在锌层上形成银层，并通过无电沉积工艺将覆盖层沉积在银层上。如果需要，可以在覆盖层上形成第二银层。在另一个实施方案中，公开了沉积钴钨合金的沉积溶液的组合物。沉积溶液包括CaWO 4 SO 4，钴源在约50mM至约500mM的范围内，络合剂在约100mM至约700mM的范围内，缓冲剂的范围约50mM至约500mM。

46. 发明授权

US06689689B1 Selective deposition process for allowing damascene-type Cu interconnect lines 有权
标题翻译：选择性沉积工艺允许镶嵌型Cu互连线
公开(公告)号：US06689689B1
公开(公告)日：2004-02-10
申请号：US09477821
申请日：2000-01-05
申请人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
发明人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
摘要翻译：通过包括在金属化特征的平坦化的上表面上选择性地沉积至少一个具有至少一个合金元素的薄层的方法来增强例如铜的平坦化在线金属化图案（例如铜）的可靠性和电迁移阻力，金属的特征，然后将至少一个薄层的至少一种合金元素的至少最少量均匀地扩散到特征的上表面下方的预定最小深度以实现与其的合金化。金属化特征的合金化部分有利地减少了电迁移。通过CMP，可以在扩散/合金化之后进行平面化，以去除至少一个薄层的任何剩余的升高，合金化或非合金化部分。本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

47. 发明授权

US06660633B1 Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed 有权
标题翻译：通过在铜表面上电镀临时铜 - 锌合金薄膜和由此形成的半导体器件来减少铜线中的电迁移的方法
公开(公告)号：US06660633B1
公开(公告)日：2003-12-09
申请号：US10083809
申请日：2002-02-26
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译：一种制造半导体器件的方法，其具有通过使用电镀设备通过电镀设置在通孔（6）中的铜箔表面（20）上电镀的临时还原氧Cu-Zn合金薄膜，所述Cu表面（20）在独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）; 并由此形成半导体器件。通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。

48. 发明授权

US06559546B1 Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure 有权
公开(公告)号：US06559546B1
公开(公告)日：2003-05-06
申请号：US10228010
申请日：2002-08-26
申请人： Krishnashree Achuthan , Sergey Lopatin
发明人： Krishnashree Achuthan , Sergey Lopatin
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76873 , H01L2221/1089 , Y10S977/701 , Y10S977/712 , Y10S977/721
摘要： For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material. In that case, a ratio of the tin ion concentration to the palladium ion concentration in the activation bath is adjusted to decrease with an amount of silicon atoms of the layer of silicon rich material deposited on the layer of diffusion barrier material. The present invention may be practiced to particular advantage when the layer of seed material and the conductive fill material are comprised of copper.

49. 发明授权

US06500743B1 Method of copper-polysilicon T-gate formation 有权
标题翻译：铜多晶硅T型栅极形成方法
公开(公告)号：US06500743B1
公开(公告)日：2002-12-31
申请号：US09651513
申请日：2000-08-30
申请人： Sergey Lopatin , Steven C. Avanzino , Matthew Buynoski
发明人： Sergey Lopatin , Steven C. Avanzino , Matthew Buynoski
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/28061 , H01L21/28114 , H01L21/28568 , H01L21/288 , H01L21/76895 , H01L29/4941 , H01L29/66545
摘要： A method for manufacturing a field effect transistor (100) includes forming a gate structure (104) on a surface of a semiconductor substrate and forming first and second spacers (126, 126) on opposing sides of the gate structure. The method further includes etching a top portion of the gate structure and the first and second spacers to define a trench (1502). Subsequently, by a damascene process, at least a portion of the trench is filed with a barrier-high conductivity metal such as copper (1604) to form a T-gate.
摘要翻译：一种用于制造场效应晶体管（100）的方法包括在半导体衬底的表面上形成栅极结构（104），并在栅极结构的相对侧上形成第一和第二间隔物（126,126）。该方法还包括蚀刻栅极结构的顶部以及第一和第二间隔物以限定沟槽（1502）。随后，通过镶嵌工艺，沟槽的至少一部分与诸如铜的阻挡 - 高导电性金属（1604）一起提供以形成T形栅极。

50. 发明授权

US06498093B1 Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect 失效
标题翻译：在互连中溶解在酸性活化溶液中的牺牲层无真空破裂的形成
公开(公告)号：US06498093B1
公开(公告)日：2002-12-24
申请号：US10052133
申请日：2002-01-17
申请人： Krishnashree Achuthan , Sergey Lopatin
发明人： Krishnashree Achuthan , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/288 , H01L21/32134 , H01L21/76802 , H01L21/76843 , H01L2221/1089 , Y10S977/715
摘要： For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution. A catalytic seed layer formed from the acidic catalytic solution is deposited on the exposed underlying material at the walls of the interconnect opening. The conductive fill for filling the interconnect opening is grown from the catalytic seed layer by electroless deposition. The present invention may be used to particular advantage when the underlying material is comprised of tantalum as a diffusion barrier material, and when the protective material of the sacrificial layer is comprised of magnesium. In that case, the acidic catalytic solution includes palladium chloride and/or tin chloride with hydrochloric acid for dissolving the sacrificial layer of protective material.
摘要翻译：为了填充形成在半导体衬底上的集成电路的互连开口，底层材料形成在互连开口的任何暴露的壁处。在互连开口的壁上的下层材料上形成保护材料的牺牲层。保护材料的下层材料和牺牲层在没有真空断裂的情况下形成。牺牲层的保护材料可溶于用于沉积催化种子层的酸性催化溶液中。具有互连开口的半导体衬底被放置在用于沉积催化种子层的酸性催化溶液中。保护材料的牺牲层通过酸性催化溶液从基底材料中溶解，使得下面的材料暴露于酸性催化溶液中。由酸性催化溶液形成的催化种子层沉积在互连开口壁上的暴露的下层材料上。用于填充互连开口的导电填料通过无电沉积从催化种子层生长。当底层材料由钽作为扩散阻挡材料构成时，并且当牺牲层的保护材料由镁构成时，本发明可被用于特别有利的方面。在这种情况下，酸性催化剂溶液包括氯化钯和/或氯化锡与盐酸溶解保护材料的牺牲层。

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