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41. 发明申请

US20080217755A1 Systems and Methods for Providing Voltage Compensation in an Integrated Circuit Chip Using a Divided Power Plane 审中-公开
标题翻译：使用分立动力平面在集成电路芯片中提供电压补偿的系统和方法
公开(公告)号：US20080217755A1
公开(公告)日：2008-09-11
申请号：US11684181
申请日：2007-03-09
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H01L23/50 , H01L21/60 , H01L21/66
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for providing power to on-chip components of an integrated circuit with improved uniformity through the use of a split power plane. One embodiment comprises a system having an integrated circuit chip, a power distribution network coupled to the integrated circuit chip, and a power plane coupled to the power distribution network. The power plane is divided into two or more separate sections, each of which is separately connected to the power distribution network. One or more power sources can be connected to the different power plane sections to apply different voltages to the different sections, thereby compensating for different resistances in the different portions of the power distribution network
摘要翻译：通过使用分离式电源平面，具有改善的均匀性，为集成电路的片上部件提供电力的系统和方法。一个实施例包括具有集成电路芯片，耦合到集成电路芯片的配电网络和耦合到配电网络的电力平面的系统。电力平面分为两个或多个分开的部分，每个部分分别连接到配电网络。一个或多个电源可以连接到不同的电源平面部分，以对不同的部分施加不同的电压，从而补偿配电网络的不同部分中的不同电阻

42. 发明申请

US20070220293A1 Systems and methods for managing power consumption in data processors using execution mode selection 审中-公开
标题翻译：使用执行模式选择来管理数据处理器中的功耗的系统和方法
公开(公告)号：US20070220293A1
公开(公告)日：2007-09-20
申请号：US11377565
申请日：2006-03-16
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/30181 , G06F9/30189 , G06F9/3836 , G06F9/3851 , G06F9/4893 , Y02D10/24
摘要： Systems and methods for identifying the power usage characteristics of software programs and using the information to determine the manner in which the software programs will be executed, thereby improving the management of power within the device executing the programs. One embodiment comprises a method for selecting execution modes of software programs to improve power consumption associated with execution of the programs. The method includes identifying a plurality of programs to be executed, where the programs may have multiple execution modes. Each program may have multiple program modules, each of which is the program configured to execute in a corresponding execution mode. Each program module has an associated power profile. The program module, hence execution mode, for each program is selected based on the associated power profile, and is then executed according to the selected execution mode.
摘要翻译：用于识别软件程序的功率使用特性并使用该信息来确定软件程序将被执行的方式的系统和方法，从而改善执行程序的设备内的电力管理。一个实施例包括用于选择软件程序的执行模式以提高与程序的执行相关联的功耗的方法。该方法包括识别要执行的多个节目，其中节目可以具有多个执行模式。每个程序可以具有多个程序模块，每个程序模块是被配置为以相应的执行模式执行的程序。每个程序模块都具有相关的电源配置文件。基于相关联的功率曲线选择每个程序的程序模块，因此执行模式，然后根据所选择的执行模式执行。

43. 发明授权

US07268629B2 System and method for lock detection of a phase-locked loop circuit 失效
标题翻译：锁相环电路锁定检测系统及方法
公开(公告)号：US07268629B2
公开(公告)日：2007-09-11
申请号：US11137072
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/00
CPC分类号： H03L7/095 , H03L7/089 , H03L7/0895 , H03L2207/14 , Y10S331/02
摘要： Systems and methods for detecting phase-locked loop circuit lock. In particular, a lock detector configured to detect PLL stability for a user-defined period of time prior to asserting a PLL-lock-detected output. Stability may be indicated by a counter inserted into a PLL circuit and arranged between a phase-frequency detector and a charge pump. Because the counter value is acted upon by the phase-frequency detector, PLL lock is indicated by counter value stability. The digital counter value may be provided to a digital charge pump and a lock detector simultaneously. The lock detector includes registers and difference detectors to determine when the difference between counter values is below a user-defined tolerance. The lock detector may include a variable timer to avoid false indications of lock which may occur when counter values are sampled with the same frequency as a fluctuation frequency of the counter value.
摘要翻译：用于检测锁相环电路锁的系统和方法。特别地，锁定检测器被配置为在断言PLL锁定检测到的输出之前检测用户定义的时间段的PLL稳定性。稳定性可以由插入PLL电路中的计数器指示并且布置在相位频率检测器和电荷泵之间。由于计数器值由相位频率检测器作用，PLL锁定由计数器值稳定性指示。数字计数器值可以同时提供给数字电荷泵和锁定检测器。锁定检测器包括寄存器和差分检测器，用于确定计数器值之间的差异何时低于用户定义的公差。锁定检测器可以包括可变定时器，以避免在以与计数器值的波动频率相同的频率对计数器值进行采样时可能发生的锁定的错误指示。

44. 发明申请

US20060267643A1 System and method for PLL control 失效
标题翻译： PLL控制的系统和方法
公开(公告)号：US20060267643A1
公开(公告)日：2006-11-30
申请号：US11137078
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/0891 , H03L7/18 , H03L7/197
摘要： Systems and methods for reducing the effects of the operation of logic on a phase-locked loop (PLL) circuit are disclosed. These systems and methods may allow a PLL circuit to compensate for the anticipated effects of an instruction before, substantially simultaneously with, or after the execution of the instruction. More particularly, logic associated with the issue of instructions in a system may provide a signal to a PLL in the system based on an instruction. The PLL may then be adjusted to compensate for the anticipated effects of the instruction based on this control signal.
摘要翻译：公开了用于减少逻辑在锁相环（PLL）电路上的操作的影响的系统和方法。这些系统和方法可以允许PLL电路在指令的执行之前，基本同时地或在执行指令之后补偿指令的预期效果。更具体地，与系统中的指令发出相关联的逻辑可以基于指令向系统中的PLL提供信号。然后可以调整PLL以补偿基于该控制信号的指令的预期效果。

45. 发明授权

US06370080B2 Semiconductor memory for logic-hybrid memory 有权
标题翻译：半导体存储器用于逻辑混合存储器
公开(公告)号：US06370080B2
公开(公告)日：2002-04-09
申请号：US09477032
申请日：2000-01-03
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1078 , G11C8/00 , G11C8/20 , G11C11/408 , G11C2207/104
摘要： This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.
摘要翻译：本发明提供了拦截异常功率信号以防止损坏半导体存储器的方法。为了实现这一点，半导体存储器包括控制来自行地址的选择的第一控制信号线，控制从列地址的选择的第二控制信号线，在预定数量的情况下，第一电压控制装置切断第一控制信号线控制信号异常，并且第二电压控制装置在预定数量的控制信号异常的情况下切断第二控制信号线。

46. 发明授权

US06370077B1 Dynamic random access memory device and semiconductor integrated circuit device 有权
公开(公告)号：US06370077B1
公开(公告)日：2002-04-09
申请号：US09545438
申请日：2000-04-07
申请人： Masaru Koyanagi , Kaoru Nakagawa , Takahiko Hara , Satoru Takase
发明人： Masaru Koyanagi , Kaoru Nakagawa , Takahiko Hara , Satoru Takase
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C8/12 , G11C11/406
摘要： A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

47. 发明授权

US6134174A Semiconductor memory for logic-hybrid memory 失效
公开(公告)号：US6134174A
公开(公告)日：2000-10-17
申请号：US949762
申请日：1997-10-14
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00 , G11C8/20 , G11C11/408
CPC分类号： G11C7/22 , G11C11/408 , G11C7/1078 , G11C8/00 , G11C8/20 , G11C2207/104
摘要： This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

48. 发明授权

US5712827A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5712827A
公开(公告)日：1998-01-27
申请号：US530725
申请日：1995-09-19
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C11/401 , G11C5/02 , G11C7/06 , G11C7/10 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C13/00 , G11C11/34
CPC分类号： G11C7/1012 , G11C11/4093 , G11C11/4096 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

49. 发明授权

US5367481A Dynamic random access memory with complementary bit lines and capacitor common line 失效
标题翻译：具有互补位线和电容公共线的动态随机存取存储器
公开(公告)号：US5367481A
公开(公告)日：1994-11-22
申请号：US985114
申请日：1992-12-03
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/404 , G11C11/4074 , G11C11/409 , G11C11/24
CPC分类号： G11C11/4074
摘要： A DRAM comprising a memory cell array having a dynamic type memory cell having one MOS transistor for transfer gate and one capacitor for data storage with one end connected to the transistor, a word line connected in common to the gate of each transistor in each row of the memory cell array, a bit line connected in common to each transistor in each column of the memory cell array, a bit line precharge circuit provided so as to precharge the bit line of the memory cell array at a predetermined timing, a capacitor common line provided so as to correspond to a pair of complementary bit lines of the memory cell array and connected in common to the other end of the capacitor of the memory cell, a capacitor common precharge circuit provided so as to precharge the capacitor common line at predetermined timing, capacitor common line transfer gates for connecting the capacitor common line to the input nodes of a sense amplifier and on/off controlled at a predetermined timing, and bit line transfer gates for connecting the input nodes of the sense amplifier and the complementary pair of bit lines, respectively, and on/off controlled at a predetermined timing.
摘要翻译：一种DRAM，包括具有一个动态型存储单元的存储单元阵列，该存储单元具有一个用于传输门的MOS晶体管和一个用于数据存储的电容器，其一端连接到该晶体管，一个字线共同连接到每一行的每个晶体管的栅极存储单元阵列，与存储单元阵列的每列中的每个晶体管共同连接的位线，设置为预定时间对存储单元阵列的位线预充电的位线预充电电路，电容器公共线被设置为对应于存储单元阵列的一对互补位线并共同连接到存储单元的电容器的另一端;电容器公共预充电电路，被设置为以预定的时间对电容器公共线预充电用于将电容器公共线连接到读出放大器的输入节点的电容器公共线传输门和在预定定时控制的导通/截止，以及位线tran 用于分别连接读出放大器的输入节点和互补的一对比特线，以及在预定定时控制的开/关。

50. 发明授权

US08531865B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08531865B2
公开(公告)日：2013-09-10
申请号：US13197950
申请日：2011-08-04
申请人： Koji Hosono , Satoru Takase
发明人： Koji Hosono , Satoru Takase
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C2013/0054
摘要： A semiconductor memory device according to the embodiment comprises a memory cell array including first line, second line crossing the first line, and memory cell containing variable resistance element provided on the intersection of the first and second lines; a data write unit operative to cause the variable resistance element to make a transition from a first resistance to a second resistance different from the first resistance; and a resistance state detection unit including an abnormality detection circuit operative to detect a transition of the resistance of the variable resistance element to a third resistance when the data write unit causes the variable resistance element to make the transition from the first resistance to the second resistance (where the third resistance the first resistance>the second resistance).
摘要翻译：根据实施例的半导体存储器件包括包括第一线，与第一线交叉的第二线的存储单元阵列和设置在第一和第二线的交叉点上的包含可变电阻元件的存储单元; 数据写入单元，用于使可变电阻元件从第一电阻转变到与第一电阻不同的第二电阻; 以及电阻状态检测单元，包括异常检测电路，当数据写入单元使可变电阻元件从第一电阻向第二电阻转变时，检测可变电阻元件的电阻向第三电阻的转变（其中第三电阻<第一电阻<第二电阻或第三电阻>第一电阻>第二电阻）。

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