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41. 发明申请

US20170110656A1 METHODS OF FORMING AN INTERCONNECTION LINE AND METHODS OF FABRICATING A MAGNETIC MEMORY DEVICE USING THE SAME 审中-公开
公开(公告)号：US20170110656A1
公开(公告)日：2017-04-20
申请号：US15227334
申请日：2016-08-03
申请人： Samsung Electronics Co., Ltd.
发明人： Jaehun Seo , Jong-Kyu Kim , Jung-Ik Oh , Inho Kim , Jongchul Park , Gwang-Hyun Baek , Hyun-woo Yang
IPC分类号： H01L43/12 , H01L43/08 , H01L21/768 , H01L43/02
CPC分类号： H01L43/12 , H01L21/02071 , H01L21/32138 , H01L27/222
摘要： Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.

42. 发明授权

US09496488B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09496488B2
公开(公告)日：2016-11-15
申请号：US14070471
申请日：2013-11-01
申请人： Samsung Electronics Co., Ltd.
发明人： Hyungjoon Kwon , Sechung Oh , Vladimir Urazaev , Ken Tokashiki , Jongchul Park , Gwang-Hyun Baek , Jaehun Seo , Sangmin Lee
IPC分类号： H01L43/08 , H01L27/22 , H01L45/00 , H01L27/24
CPC分类号： H01L43/08 , G11C11/161 , H01L27/222 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L43/02 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
摘要翻译：提供半导体器件及其制造方法。半导体器件可以包括下部布线，穿过下部布线的上部布线，在下部布线和上部布线之间的交叉处提供的选择元件以及设置在选择元件和上部布线之间的存储元件。每个存储元件可以包括具有大于底部宽度的顶部宽度的下部电极，以及包括堆叠在下部电极的顶表面上并且具有圆形边缘的多个磁性层的数据存储层。

43. 外观设计

USD1000404S1 Electronic device 有权
公开(公告)号：USD1000404S1
公开(公告)日：2023-10-03
申请号：US29802703
申请日：2021-08-06
申请人： Samsung Electronics Co., Ltd.
设计人： Jaehun Seo
摘要： FIG. 1 is a front perspective view of a first embodiment of an electronic device showing my new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof;
FIG. 8 is a rear perspective view thereof;
FIG. 9 is a front perspective view of a second embodiment of an electronic device showing my new design;
FIG. 10 is a front view thereof;
FIG. 11 is a rear view thereof;
FIG. 12 is a left-side view thereof;
FIG. 13 is a right-side view thereof;
FIG. 14 is a top view thereof;
FIG. 15 is a bottom view thereof;
FIG. 16 is a rear perspective view thereof;
FIG. 17 is a front perspective view of a third embodiment of an electronic device showing my new design;
FIG. 18 is a front view thereof;
FIG. 19 is a rear view thereof;
FIG. 20 is a left-side view thereof;
FIG. 21 is a right-side view thereof;
FIG. 22 is a top view thereof;
FIG. 23 is a bottom view thereof;
FIG. 24 is a rear perspective view thereof;
FIG. 25 is a front perspective view of a fourth embodiment of an electronic device showing my new design;
FIG. 26 is a front view thereof;
FIG. 27 is a rear view thereof;
FIG. 28 is a left-side view thereof;
FIG. 29 is a right-side view thereof;
FIG. 30 is a top view thereof;
FIG. 31 is a bottom view thereof;
FIG. 32 is a rear perspective view thereof;
FIG. 33 is a front perspective view of a fifth embodiment of an electronic device showing my new design;
FIG. 34 is a front view thereof;
FIG. 35 is a rear view thereof;
FIG. 36 is a left-side view thereof;
FIG. 37 is a right-side view thereof;
FIG. 38 is a top view thereof;
FIG. 39 is a bottom view thereof;
FIG. 40 is a rear perspective view thereof;
FIG. 41 is a front perspective view of a sixth embodiment of an electronic device showing my new design;
FIG. 42 is a front view thereof;
FIG. 43 is a rear view thereof;
FIG. 44 is a left-side view thereof;
FIG. 45 is a right-side view thereof;
FIG. 46 is a top view thereof;
FIG. 47 is a bottom view thereof;
FIG. 48 is a rear perspective view thereof;
FIG. 49 is a front perspective view of a seventh embodiment of an electronic device showing my new design;
FIG. 50 is a front view thereof;
FIG. 51 is a rear view thereof;
FIG. 52 is a left-side view thereof;
FIG. 53 is a right-side view thereof;
FIG. 54 is a top view thereof;
FIG. 55 is a bottom view thereof;
FIG. 56 is a rear perspective view thereof;
FIG. 57 is a front perspective view of an eighth embodiment of an electronic device showing my new design;
FIG. 58 is a front view thereof;
FIG. 59 is a rear view thereof;
FIG. 60 is a left-side view thereof;
FIG. 61 is a right-side view thereof;
FIG. 62 is a top view thereof;
FIG. 63 is a bottom view thereof;
FIG. 64 is a rear perspective view thereof;
FIG. 65 is a front perspective view of a ninth embodiment of an Electronic device showing my new design;
FIG. 66 is a front view thereof;
FIG. 67 is a rear view thereof;
FIG. 68 is a left-side view thereof;
FIG. 69 is a right-side view thereof;
FIG. 70 is a top view thereof;
FIG. 71 is a bottom view thereof;
FIG. 72 is a rear perspective view thereof;
FIG. 73 is a front perspective view of a tenth embodiment of an electronic device showing my new design;
FIG. 74 is a front view thereof;
FIG. 75 is a rear view thereof;
FIG. 76 is a left-side view thereof;
FIG. 77 is a right-side view thereof;
FIG. 78 is a top view thereof;
FIG. 79 is a bottom view thereof; and,
FIG. 80 is a rear perspective view thereof.
The evenly-dashed broken lines in the drawings illustrate portions of the electronic device that form no part of the claimed design.