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41. 发明授权

US07836260B2 Low complexity speculative multithreading system based on unmodified microprocessor core 有权
标题翻译：基于未修改的微处理器核心的低复杂度推测性多线程系统
公开(公告)号：US07836260B2
公开(公告)日：2010-11-16
申请号：US12147914
申请日：2008-06-27
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

42. 发明授权

US07461383B2 Method and apparatus for efficient performance monitoring of a large number of simultaneous events 失效
标题翻译：用于高效率监测大量同时事件的方法和装置
公开(公告)号：US07461383B2
公开(公告)日：2008-12-02
申请号：US11507307
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.
摘要翻译：一种用于监视大量同时事件的系统实现了具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值混合计数器阵列的位。第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。数据传输子系统另外启用以下一个或多个：通过窄总线对第一和第二计数器部分中的计数值进行读访问或写入访问，用于初始化和确定计数状态的读/写访问响应于处理器设备请求的被监视事件类型的值。

43. 发明授权

US09727336B2 Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers 有权
公开(公告)号：US09727336B2
公开(公告)日：2017-08-08
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

44. 发明申请

US20130262821A1 PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING 有权
标题翻译：与预定时间优化的指令序列缓存执行预定时间优化的指令
公开(公告)号：US20130262821A1
公开(公告)日：2013-10-03
申请号：US13432357
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/384
摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.
摘要翻译：一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。

45. 发明申请

US20130212139A1 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS 有权
标题翻译：混合精度估计指标计算精度高精度结果进行精确输入
公开(公告)号：US20130212139A1
公开(公告)日：2013-08-15
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/483 , G06F7/499 , G06F17/10
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.
摘要翻译：提供了一种用于执行混合精度估计的技术。处理电路接收具有宽精度值的第一精度的输入。处理电路基于宽精度值的输入，计算与窄精度值对应的输出指数范围内的输出。

46. 发明申请

US20130086362A1 Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information 有权
标题翻译：基于具有操作数首次使用信息的建筑计算机指令集管理寄存器缓存
公开(公告)号：US20130086362A1
公开(公告)日：2013-04-04
申请号：US13251426
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/312
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译：执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或前缀指令执行的目标寄存器。

47. 发明申请

US20130073836A1 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY 有权
公开(公告)号：US20130073836A1
公开(公告)日：2013-03-21
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

48. 发明授权

US08127078B2 High performance unaligned cache access 有权
标题翻译：高性能未对齐缓存访问
公开(公告)号：US08127078B2
公开(公告)日：2012-02-28
申请号：US12572416
申请日：2009-10-02
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0886
摘要： A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache line, and a second cache array coupled to an alignment unit is configured to output a second cache entry associated with the alignment cache line. The alignment unit coupled to the address decoder selects either the target cache line or a neighbor cache line proximate the target cache line as an alignment cache line output. Selection of either the target cache line or a neighbor cache line is based on an alignment bit in the memory address. A tag array cache is split into even and odd cache lines tags, and provides one or two tags for every cache access.
摘要翻译：一种高速缓冲存储器件及其操作方法。高速缓冲存储器设备的一个实施例包括解码存储器地址并选择目标高速缓存行的地址译码器。第一高速缓存阵列被配置为输出与目标高速缓存行相关联的第一高速缓存条目，并且耦合到对准单元的第二高速缓存阵列被配置为输出与对准高速缓存行相关联的第二高速缓存条目。耦合到地址解码器的对准单元选择目标高速缓存线或邻近目标高速缓存行的相邻高速缓存行作为对准高速缓存行输出。目标高速缓存行或相邻高速缓存行的选择基于存储器地址中的对齐位。标签数组高速缓存分为偶数和奇数缓存行标签，并为每个高速缓存访问提供一个或两个标签。

49. 发明授权

US07620756B2 Method and apparatus for updating wide storage array over a narrow bus 有权
标题翻译：用于在窄总线上更新宽存储阵列的方法和装置
公开(公告)号：US07620756B2
公开(公告)日：2009-11-17
申请号：US11507306
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译：一种用于从窄总线（m位，其中m

50. 发明授权

US09354874B2 Scalable decode-time instruction sequence optimization of dependent instructions 有权
公开(公告)号：US09354874B2
公开(公告)日：2016-05-31
申请号：US13251409
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3005 , G06F9/30127 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.

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