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    • 41. 发明授权
    • Distributed stateful intrusion detection for voice over IP
    • IP语音分布式状态入侵检测
    • US09178898B2
    • 2015-11-03
    • US11854439
    • 2007-09-12
    • Sachin GargNavjot SinghYu-Sung Wu
    • Sachin GargNavjot SinghAkshay AdhikariYu-Sung Wu
    • G06F21/00H04L29/06
    • H04L63/1416H04L65/1006
    • An apparatus and method for detecting intrusions in Voice over Internet Protocol systems with distributed stateful intrusion detection. When a Session Initiation Protocol (SIP) signal is received as an application-layer protocol signal, the received application-layer protocol signal is distributed to a first finite-state machine and to a second finite-state machine. A data processing system detects that the application-layer protocol enters a first application-layer protocol state S1 at a first node at a first time, determines whether the application-layer protocol fails to enter a second application-layer protocol state S2 at a second node within δ seconds, a positive real number, and generates a signal that indicates a potential intrusion in response to the determination.
    • 一种用于通过分布式状态入侵检测来检测基于因特网协议的语音系统中的入侵的装置和方法。 当接收到会话发起协议(SIP)信号作为应用层协议信号时,接收的应用层协议信号被分配到第一有限状态机和第二有限状态机。 数据处理系统检测到第一应用层协议在第一节点处进入第一应用层协议状态S1,确定应用层协议是否在第二时刻不能进入第二应用层协议状态S2 δ秒内的节点,正实数,并产生指示响应于确定的潜在入侵的信号。
    • 42. 发明授权
    • Methods and apparatus for interfacing between a host processor and a coprocessor
    • 用于在主处理器和协处理器之间进行接口的方法和装置
    • US08095699B2
    • 2012-01-10
    • US11542092
    • 2006-09-29
    • Sachin GargPaul D. Krivacek
    • Sachin GargPaul D. Krivacek
    • G06F3/00
    • G06F13/126G06F9/3881G06F13/4273Y02D10/14Y02D10/151
    • An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.
    • 提供了在主处理器和外部协处理器之间传送数据的接口。 接口可以在几种写入模式下操作,其中在第一写入模式中,写入操作在两个时钟周期内在该接口上传送,并且在第二写入模式中,写入操作在单个时钟周期内通过该接口传送。 接口可以执行由主处理器发起的第一读取操作和由外部协处理器发起的第二读取操作。 接口可以包括用于存储读取和写入操作的缓冲器和时钟门,以选择性地关闭提供给缓冲器的时钟信号,以将数据传入和传出缓冲器。 可以修改可选择的优先级方案,以便在读取和写入操作都排队等待传输时,在优先级之间选择控制在接口上传送操作的优先级。
    • 43. 发明授权
    • Message log analysis for system behavior evaluation
    • 系统行为评估的消息日志分析
    • US08073806B2
    • 2011-12-06
    • US11874161
    • 2007-10-17
    • Sachin GargNavjot SinghShalini YajnikRanjith VasireddySridhar Vasireddy, legal representative
    • Sachin GargNavjot SinghShalini YajnikRanjith Vasireddy
    • G06F15/00G06F15/18
    • H04L12/66
    • A technique is disclosed that enables the run-time behavior of a data-processing system to be analyzed and, in many cases, to be predicted. In particular, the illustrative embodiment of the present invention comprises i) transforming the messages that constitute an unstructured log into a numerical series and ii) applying a time-series analysis on the resultant series for the purpose of pattern detection. Indeed, it is recognized in the illustrative embodiment that the problem really is to detect patterns that depict aspects of system behavior, regardless of the textual content of the individual log messages. In other words, by analyzing the totality of the messages in the log or logs—as opposed to looking for pre-defined patterns of the individual messages—system behavior can be mapped and understood. The mapping helps in characterizing the system for the purposes of predicting failure, determining the time required to reach stability during failure recovery, and so forth.
    • 公开了一种能够分析数据处理系统的运行时行为并且在许多情况下被预测的技术。 特别地,本发明的说明性实施例包括:i)将构成非结构化日志的消息变换为数字序列,以及ii)为了模式检测的目的,对所得到的序列应用时间序列分析。 实际上,在说明性实施例中认识到,问题确实是检测描绘系统行为方面的模式,而不管各个日志消息的文本内容如何。 换句话说,通过分析日志或日志中的消息的总体,而不是寻找单个消息的预定义模式,可以映射和理解系统行为。 映射有助于表征系统的目的是为了预测故障,确定在故障恢复期间达到稳定所需的时间等等。
    • 48. 发明授权
    • Stateful and cross-protocol intrusion detection for voice over IP
    • 针对IP语音的状态和跨协议入侵检测
    • US07451486B2
    • 2008-11-11
    • US10955594
    • 2004-09-30
    • Sachin GargNavjot SinghTimothy Kohchih TsaiYu-Sung WuSaurabh Bagchi
    • Sachin GargNavjot SinghTimothy Kohchih TsaiYu-Sung WuSaurabh Bagchi
    • H04L9/00H04L12/22
    • H04L63/1433
    • A method for detecting intrusions that employ messages of two or more protocols is disclosed. Such intrusions might occur in Voice over Internet Protocol (VoIP) systems, as well as in systems in which two or more protocols support some service other than VoIP. In the illustrative embodiment of the present invention, a stateful intrusion-detection system is capable of employing rules that have cross-protocol pre-conditions. The illustrative embodiment can use such rules to recognize a variety of VoIP-based intrusion attempts, such as call hijacking, BYE attacks, etc. In addition, the illustrative embodiment is capable of using such rules to recognize other kinds of intrusion attempts in which two or more protocols support a service other than VoIP. The illustrative embodiment also comprises a stateful firewall that is capable of employing rules with cross-protocol pre-conditions.
    • 公开了一种用于检测采用两种或多种协议的消息的入侵的方法。 这种入侵可能发生在语音互联网协议(VoIP)系统中,以及在两个或多个协议支持VoIP之外的一些服务的系统中。 在本发明的说明性实施例中,状态入侵检测系统能够采用具有交叉协议前提条件的规则。 说明性实施例可以使用这样的规则来识别各种基于VoIP的入侵尝试,例如呼叫劫持,BYE攻击等。此外,说明性实施例能够使用这样的规则来识别其他种类的入侵尝试,其中两个 或更多的协议支持VoIP以外的服务。 说明性实施例还包括能够使用具有交叉协议前提条件的规则的有状态防火墙。
    • 49. 发明申请
    • Signal Watermarking in the Presence of Encryption
    • 信号水印加密存在
    • US20080199009A1
    • 2008-08-21
    • US11675352
    • 2007-02-15
    • Akshay AdhikariSachin GargAnjur Sundaresan KrishnakumarNavjot Singh
    • Akshay AdhikariSachin GargAnjur Sundaresan KrishnakumarNavjot Singh
    • H04K1/02
    • G06T1/0021G10L19/018H04H20/28H04H20/31H04H60/23H04H2201/50H04L9/065H04L2209/30H04L2209/608
    • A method is disclosed that enables the transmission of a digital message along with a corresponding information signal, such as audio or video. The supplemental information contained in digital messages can be used for a variety of purposes, such as enabling or enhancing packet authentication. In particular, a telecommunications device that is processing an information signal from its user, such as a speech signal, encrypts the information signal by performing a bitwise exclusive-or of an encryption key stream with the information signal stream. The device, such as a telecommunications endpoint, then intersperses the bits of the digital message throughout the encrypted signal in place of those bits overwritten, in a process referred to as “watermarking.” The endpoint then transmits the interspersed digital message bits as part of a composite signal that also comprises the encrypted information bits. No additional bits are appended to the packet to be transmitted, thereby addressing compatibility issues.
    • 公开了一种能够传送数字消息以及对应的信息信号(诸如音频或视频)的方法。 数字消息中包含的补充信息可用于各种目的,例如启用或增强数据包认证。 特别地,正在处理来自其用户的信息信号(例如语音信号)的电信设备通过执行与信息信号流的按位异或加密密钥流来加密信息信号。 在称为“水印”的过程中,诸如电信端点的设备然后在整个加密信号中分散数字消息的位,以代替被覆盖的位。 然后,端点将散布的数字消息比特作为还包括加密信息比特的复合信号的一部分进行发送。 没有额外的位附加到要发送的数据包,从而解决兼容性问题。
    • 50. 发明申请
    • Methods and apparatus for interfacing between a host processor and a coprocessor
    • 用于在主处理器和协处理器之间进行接口的方法和装置
    • US20080155135A1
    • 2008-06-26
    • US11542092
    • 2006-09-29
    • Sachin GargPaul D. Krivacek
    • Sachin GargPaul D. Krivacek
    • G06F13/28
    • G06F13/126G06F9/3881G06F13/4273Y02D10/14Y02D10/151
    • In one aspect, an interface adapted to transfer data between a host processor and an external coprocessor is provided. The interface may be adapted to operate in a plurality of write modes, wherein in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. In another aspect, the interface is adapted to perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. In another aspect, the interface includes a plurality of buffers to store read and write operations and a plurality of clock gates to selectively gate of clock signals provided to the plurality of buffers to synchronize transfer of data into and out of the buffers. In another aspect, the interface includes a selectable priority scheme capable of being modified to select between a plurality of priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.
    • 在一个方面,提供一种适于在主处理器和外部协处理器之间传送数据的接口。 该接口可以适于以多种写入模式操作,其中在第一写入模式中,写入操作在两个时钟周期内在该接口上传送,并且在第二写入模式中,写入操作以单个时钟在该接口上传送 周期。 在另一方面,接口适于执行由主机处理器发起的第一读取操作和由外部协处理器发起的第二读取操作。 在另一方面,接口包括多个用于存储读取和写入操作的缓冲器以及多个时钟门,用于选择性地提供给多个缓冲器的时钟信号的门,以同步数据传入和传出缓冲器。 在另一方面,接口包括可选择的优先级方案,其能够被修改为在读取和写入操作都排队等待传送时控制在接口上传送操作的优先级的多个优先级之间进行选择。