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41. 发明授权

US08105962B2 Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach 有权
标题翻译：方法和包括用于在双应力衬垫方法中减少应力松弛的保护层的半导体器件
公开(公告)号：US08105962B2
公开(公告)日：2012-01-31
申请号：US12131429
申请日：2008-06-02
申请人： Kai Frohberg , Frank Feustel , Thomas Werner , Uwe Griebenow
发明人： Kai Frohberg , Frank Feustel , Thomas Werner , Uwe Griebenow
IPC分类号： H01L21/31
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.
摘要翻译：通过在双重应力衬垫方法中提供用于抑制拉应力介电材料中的应力松弛的保护层，可以增加N沟道晶体管的性能，同时保持与常规双应力衬垫方法的高度兼容性。

42. 发明申请

US20100164123A1 LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件金属化系统中通过底部的局部硅化
公开(公告)号：US20100164123A1
公开(公告)日：2010-07-01
申请号：US12640444
申请日：2009-12-17
申请人： Tobias Letz , Frank Feustel
发明人： Tobias Letz , Frank Feustel
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76814 , H01L21/76826 , H01L21/76849 , H01L21/76867 , H01L21/76886
摘要： Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.
摘要翻译：通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

43. 发明申请

US20100133699A1 MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS 审中-公开
标题翻译：包括与VIAS共同形成的空气GAPS的金属结构的微结构设备
公开(公告)号：US20100133699A1
公开(公告)日：2010-06-03
申请号：US12619816
申请日：2009-11-17
申请人： Thomas Werner , Kai Frohberg , Frank Feustel
发明人： Thomas Werner , Kai Frohberg , Frank Feustel
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which respective via openings are also formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may be efficiently reduced without adding additional process complexity.
摘要翻译：基于形成相应通孔的图案化顺序，可以在微结构器件的金属化层中形成气隙。此后，通孔和气隙可以通过沉积工艺封闭，而不会明显地影响相应的开口的内部。此后，可以通过在保持覆盖的气隙的完整性的同时形成相应的沟槽来继续进一步的处理。因此，可以有效地降低层间绝缘材料的相对介电常数，而不增加额外的工艺复杂性。

44. 发明申请

US20090221123A1 METHOD FOR INCREASING PENETRATION DEPTH OF DRAIN AND SOURCE IMPLANTATION SPECIES FOR A GIVEN GATE HEIGHT 有权
标题翻译：用于增加浇口高度的排水深度和源植入物种的渗透深度的方法
公开(公告)号：US20090221123A1
公开(公告)日：2009-09-03
申请号：US12205221
申请日：2008-09-05
申请人： Uwe Griebenow , Kai Frohberg , Frank Feustel , Thomas Werner
发明人： Uwe Griebenow , Kai Frohberg , Frank Feustel , Thomas Werner
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7848
摘要： The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.
摘要翻译：漏极和源极区域的厚度可以通过用适合的半导体材料重新填充空腔的腔蚀刻来减小，其中，在外延生长之前，可以进行注入工艺以便形成深的漏极和源极对于给定的关键栅极高度，没有有助于不期望的沟道掺杂的区域。在其他情况下，可以通过执行用于引入深漏极和源极区域的倾斜注入步骤来增强栅电极结构的有效离子阻挡长度。

45. 发明申请

US20090194825A1 SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件中的自对准接触结构
公开(公告)号：US20090194825A1
公开(公告)日：2009-08-06
申请号：US12176469
申请日：2008-07-21
申请人： Thomas Werner , Frank Feustel , Kai Frohberg
发明人： Thomas Werner , Frank Feustel , Kai Frohberg
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28518 , H01L21/76232
摘要： By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.
摘要翻译：通过形成在由有源区的半导体材料限定的高度水平之上延伸的隔离结构，相应的凹槽可以与完成基本晶体管结构的栅电极结构相结合。这些凹部可以随后用适当的接触材料填充，从而以自对准的方式形成大面积的接触，而不需要层间绝缘材料的沉积和图案化。此后，例如，可以基于公知的技术形成第一金属化层，其中金属线可以直接连接到相应的“大面积”接触元件。

46. 发明申请

US20090140431A1 HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中具有低纵横比接触的混合接触结构
公开(公告)号：US20090140431A1
公开(公告)日：2009-06-04
申请号：US12131332
申请日：2008-06-02
申请人： Frank Feustel , Kai Frohberg , Thomas Werner
发明人： Frank Feustel , Kai Frohberg , Thomas Werner
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76807 , H01L21/76816 , H01L23/53238 , H01L23/53266 , H01L29/665 , H01L29/66507 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure.
摘要翻译：通过形成作为双镶嵌结构的半导体器件的第一金属化层，可以基于显着减小的纵横比来形成接触元件，从而增强工艺稳定性并且还提高接触结构的电性能。

47. 发明申请

US20090085173A1 SIDEWALL PROTECTION LAYER 审中-公开
标题翻译：防护层
公开(公告)号：US20090085173A1
公开(公告)日：2009-04-02
申请号：US12056356
申请日：2008-03-27
申请人： Juergen Boemmels , Frank Feustel , Ralf Richter
发明人： Juergen Boemmels , Frank Feustel , Ralf Richter
IPC分类号： H01L23/58 , H01L21/311 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due to the porous nature of the low-k dielectric materials. Thus, smooth and dense sidewalls cannot be achieved, which is a prerequisite for an effective barrier layer, which prevents copper from being diffused into the low-k dielectric material. As a consequence, process tolerances are high and the reliability of the semiconductor device is reduced. The present disclosure overcomes these drawbacks by a surface treatment of the sidewalls of trenches and vias in order to densify the surface such that the following barrier layer may more effectively prevent copper from diffusing into the low-k or ultra high-k dielectric material.
摘要翻译：本公开一般涉及在半导体器件中形成金属化层。特别地，本公开涉及在低k电介质层中的镶嵌技术。由于低k介电材料的多孔性质，低k电介质材料中的蚀刻沟槽和通孔导致沟槽和通孔的不均匀和多孔的侧壁。因此，不能实现平滑和致密的侧壁，这是有效阻挡层的先决条件，其阻止铜扩散到低k电介质材料中。因此，工艺公差高，半导体器件的可靠性降低。本公开通过沟槽和通孔的侧壁的表面处理克服了这些缺点，以便使表面致密化，使得后续阻挡层可以更有效地防止铜扩散到低k或超高k电介质材料中。

48. 发明申请

US20090032961A1 SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE 审中-公开
标题翻译：在互连结构中具有局部增强电阻率的半导体器件
公开(公告)号：US20090032961A1
公开(公告)日：2009-02-05
申请号：US12036362
申请日：2008-02-25
申请人： Frank Feustel , Tobias Letz , Thomas Werner
发明人： Frank Feustel , Tobias Letz , Thomas Werner
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76814 , H01L21/76825 , H01L21/76849 , H01L21/76867 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process.
摘要翻译：通过在通孔和金属线之间的过渡或接触区域以高度局部化的方式形成合金，可以显着减少形成电迁移诱导的浅空隙的可能性，同时不会过度地影响金属线的整体电阻率。在一个说明性实施例中，无电沉积工艺可以在无电镀工艺的基础上在暴露的金属区域上提供合金形成物质。

49. 发明授权

US07462563B2 Method of forming an etch indicator layer for reducing etch non-uniformities 有权
标题翻译：形成蚀刻指示剂层以减少蚀刻非均匀性的方法
公开(公告)号：US07462563B2
公开(公告)日：2008-12-09
申请号：US11688280
申请日：2007-03-20
申请人： Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/26506 , H01L21/3065 , H01L21/31116 , H01L21/76802 , H01L21/76808 , H01L21/76825 , H01L22/26 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.
摘要翻译：通过在形成待图案化的材料层之后并入蚀刻控制材料，可以使用具有高度显着的辐射波长的适当材料来在蚀刻工艺期间产生独特的端点检测信号。有利地，该材料可以通过离子注入并入，与蚀刻非均匀性相比，其提供了降低的不均匀性，而植入工艺提供了引入甚至非常“异乎寻常”的植入物种的潜力。在一些实施例中，可以增加双镶嵌结构的图案化的基板到基板的均匀性。

50. 发明申请

US20080160762A1 METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION 审中-公开
标题翻译：保护外部污染金属层的方法
公开(公告)号：US20080160762A1
公开(公告)日：2008-07-03
申请号：US11778291
申请日：2007-07-16
申请人： Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/443
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76861 , H01L21/76873
摘要： In order to avoid the contamination of a seed layer, which is typically highly reactive with the external atmosphere, during the formation of interconnect structures in a semiconductor device, a protective layer is formed. The protective layer may be comprised of oxide formed in an oxidizing ambient prior to transporting the semiconductor device to a subsequent process tool.
摘要翻译：为了避免在半导体器件形成互连结构期间通常与外部大气反应的种子层的污染，形成保护层。在将半导体器件传送到随后的处理工具之前，保护层可以由在氧化环境中形成的氧化物构成。

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