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41. 发明授权

US09098932B2 Graphics processing logic with variable arithmetic logic unit control and method therefor 有权
标题翻译：具有可变算术逻辑单元控制的图形处理逻辑及其方法
公开(公告)号：US09098932B2
公开(公告)日：2015-08-04
申请号：US11161674
申请日：2005-08-11
申请人： Michael Mantor
发明人： Michael Mantor
IPC分类号： G06T15/00 , G06F11/20
CPC分类号： G06T15/005 , G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.
摘要翻译：简而言之，图形数据处理逻辑包括多个并行算术逻辑单元（ALU），诸如浮点处理器或任何其它合适的逻辑，其在像素数据和顶点数据（或两者）中的至少一个上作为向量处理器，以及可编程存储元件，其包含表示多个算术逻辑单元中的哪一个不接收用于处理的数据的数据。图形数据处理逻辑还包括并行ALU数据打包逻辑，其可操作地耦合到多个算术逻辑处理单元和可编程存储元件，以仅对由可编程存储元件中的数据标识的多个算术逻辑单元打包数据被启用。

42. 发明授权

US08972693B2 Hardware managed allocation and deallocation evaluation circuit 有权
标题翻译：硬件管理分配和释放评估电路
公开(公告)号：US08972693B2
公开(公告)日：2015-03-03
申请号：US13433901
申请日：2012-03-29
申请人： Laurent Lefebvre , Michael Mantor
发明人： Laurent Lefebvre , Michael Mantor
IPC分类号： G06F12/00
CPC分类号： G06F12/023 , G06F2212/1016 , Y02D10/13
摘要： A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than using memory polling to ensure that enough space is available in memory locations for, for example, write instructions, the techniques disclosed herein provide a system and method to automate this evaluation mechanism in environments such as data-parallel processing to efficiently check available space in memory locations before instructions such as write threads are allowed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.
摘要翻译：提供了一种用于提高并行处理中的效率，功率和带宽消耗的系统和方法。不是使用存储器轮询来确保在例如写指令的存储器位置中有足够的空间可用，本文公开的技术提供了一种在诸如数据并行处理之类的环境中自动化该评估机制的系统和方法，以有效地检查可用空间在诸如写入线程的指令被允许之前的存储单元中。这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

43. 发明申请

US20130262834A1 Hardware Managed Ordered Circuit 有权
标题翻译：硬件管理有序电路
公开(公告)号：US20130262834A1
公开(公告)日：2013-10-03
申请号：US13433939
申请日：2012-03-29
申请人： Laurent Lefebvre , Michael Mantor
发明人： Laurent Lefebvre , Michael Mantor
IPC分类号： G06F9/30
CPC分类号： G06F9/38 , G06F9/30 , G06F9/3836 , G06F9/3851 , G06F9/3885 , G06F9/3887
摘要： A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than requiring memory polling to ensure ordered execution of processes or threads, the techniques disclosed herein provide a system and method to allow any process or thread to run out of order as long as needed, but ensure ordered execution of multiple ordered instructions when needed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.
摘要翻译：提供了一种用于提高并行处理中的效率，功率和带宽消耗的系统和方法。不需要内存轮询来确保进程或线程的有序执行，本文公开的技术提供了一种系统和方法，以允许任何进程或线程在需要时长时间运行，但是在需要时确保有序执行多个有序指令。这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

44. 发明授权

US06967664B1 Method and apparatus for primitive processing in a graphics system 有权
标题翻译：用于在图形系统中进行原始处理的方法和装置
公开(公告)号：US06967664B1
公开(公告)日：2005-11-22
申请号：US09552932
申请日：2000-04-20
申请人： Ralph C. Taylor , Michael Mantor , Michael A. Mang
发明人： Ralph C. Taylor , Michael Mantor , Michael A. Mang
IPC分类号： G09G5/02
CPC分类号： G06T15/30
摘要： A method and apparatus for processing graphics primitives that includes a trivial discard guard band. Such a trivial discard guard band is used for comparison operations with the vertices of graphics primitives to determine whether the graphics primitives can be trivially discarded such that no further processing of the primitives is performed. The trivial discard guard band may be based on the specific dimensions of primitives such as one-half of the width of the line primitives or the radial dimension of point primitives such that the rasterization area of such primitives is taken into account when trivial discard decisions are performed.
摘要翻译：一种用于处理包括平凡丢弃保护带的图形图元的方法和装置。这样一个平凡的丢弃保护带用于与图形基元的顶点的比较操作，以确定是否可以平均地丢弃图形基元，使得不执行对图元的进一步处理。平凡的丢弃保护带可以基于诸如线基元的宽度的一半或点基元的径向尺寸的基元的特定尺寸，使得当简单的丢弃决定是这样的原理时，考虑到这样的图元的光栅化区域执行。

45. 发明授权

US6044457A State machine controller capable of producing result per clock cycle using wait/no wait and empty signals to control the advancing of data in pipeline 失效
标题翻译：状态机控制器能够使用等待/无等待和空信号产生每个时钟周期的结果，以控制管道中的数据的前进
公开(公告)号：US6044457A
公开(公告)日：2000-03-28
申请号：US54820
申请日：1998-04-03
申请人： Michael Mantor , John Pedicone , Steven Manno , Val Gene Cook
发明人： Michael Mantor , John Pedicone , Steven Manno , Val Gene Cook
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3869 , G06F9/3824
摘要： A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The state machine controller can produce a result per clock pulse, schedule new data to be processed before completion of the processing of previous data to prevent bubbles or interruptions in the data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, and can resume one clock operation on the clock pulse when the hold is removed.
摘要翻译：一种状态机控制器，可用于获取实时计算机图像生成系统的数据，并为系统控制时钟的每个时钟间隔提供有效数据。状态机控制器可以产生每个时钟脉冲的结果，在完成先前数据的处理之前调度要处理的新数据，以防止数据流水线中的气泡或中断，并且如果从后期的流水线级，并且当保持被移除时，可以在时钟脉冲上恢复一个时钟操作。

46. 发明授权

US09304772B2 Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme 有权
标题翻译：基于波前优先级，操作计数器和排序方案订购线程波前指令操作
公开(公告)号：US09304772B2
公开(公告)日：2016-04-05
申请号：US13433939
申请日：2012-03-29
申请人： Laurent Lefebvre , Michael Mantor
发明人： Laurent Lefebvre , Michael Mantor
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/38 , G06F9/30 , G06F9/3836 , G06F9/3851 , G06F9/3885 , G06F9/3887
摘要： A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than requiring memory polling to ensure ordered execution of processes or threads in wavefronts, the techniques disclosed herein provide a system and method to allow any process or thread in a wavefront to run out of order as long as needed, but ensure ordered execution of multiple ordered instructions when needed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.
摘要翻译：提供了一种用于提高并行处理中的效率，功率和带宽消耗的系统和方法。不需要内存轮询来确保波前的进程或线程的有序执行，本文公开的技术提供一种系统和方法，以允许波阵面中的任何进程或线程在需要时长时间运行，但确保有序执行多个有需要时的指示。这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

47. 发明授权

US09170820B2 Syscall mechanism for processor to processor calls 有权
标题翻译：用于处理器到处理器调用的Syscall机制
公开(公告)号：US09170820B2
公开(公告)日：2015-10-27
申请号：US13327443
申请日：2011-12-15
申请人： Norman Rubin , Michael Mantor
发明人： Norman Rubin , Michael Mantor
IPC分类号： G06F15/00 , G06T1/00 , G06F9/38 , G06T1/20
CPC分类号： G06F9/3877 , G06T1/20
摘要： Provided is a method for processing system calls from a GPU to a CPU. The method includes a GPU storing a plurality of tasks in a memory, with each task representing a function to be performed on the CPU. The method also includes generating a CPU interrupt, and processing of the stored plurality of tasks by the CPU.
摘要翻译：提供了一种处理从GPU到CPU的系统调用的方法。该方法包括在存储器中存储多个任务的GPU，每个任务表示要在CPU上执行的功能。该方法还包括产生CPU中断以及由CPU处理所存储的多个任务。

48. 发明授权

US08190826B2 Write combining cache with pipelined synchronization 有权
标题翻译：将组合缓存与流水线同步相结合
公开(公告)号：US08190826B2
公开(公告)日：2012-05-29
申请号：US12128149
申请日：2008-05-28
申请人： Laurent Lefebvre , Michael Mantor , Robert Hankinson
发明人： Laurent Lefebvre , Michael Mantor , Robert Hankinson
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0855
摘要： Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.
摘要翻译：这里描述了在组合缓存中的流水线同步的系统和方法。将数据发送到存储器以实现高速缓存的流水线同步的实施例包括获得用于与所述存储器的事务的多个同步事件，计算所述事件与存储在所述高速缓存的一个或多个高速缓存行中的所述数据之间的一个或多个匹配存储与所述匹配关联的事件的事件时间戳，基于所述事件时间戳生成一个或多个优先级值，并基于所述优先级值同时发送所述数据到所述存储器。

49. 发明授权

US07111156B1 Method and apparatus for multi-thread accumulation buffering in a computation engine 失效
标题翻译：计算引擎中多线程累加缓冲的方法和装置
公开(公告)号：US07111156B1
公开(公告)日：2006-09-19
申请号：US09556473
申请日：2000-04-21
申请人： Michael Andrew Mang , Michael Mantor
发明人： Michael Andrew Mang , Michael Mantor
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30101
摘要： A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein each of the plurality of accumulation registers corresponds to a different thread of the plurality of threads. The contents of each of the plurality of accumulation registers can be selected as an input to the adder such that the present accumulated value can be added to a subsequently calculated produce to generate a new accumulated value.
摘要翻译：提出了一种用于增强执行乘法和累加操作的多线程处理系统中指令排序灵活性的方法和装置。提供多个累加寄存器用于存储加法器的结果，其中多个累加寄存器中的每一个对应于多个线程的不同线程。可以将多个累加寄存器中的每一个的内容选择为加法器的输入，使得当前累积值可以被添加到随后计算的乘积以产生新的累加值。

50. 发明申请

US20060164429A1 3-D rendering texture caching scheme 审中-公开
公开(公告)号：US20060164429A1
公开(公告)日：2006-07-27
申请号：US11344030
申请日：2006-01-30
申请人： Michael Mantor , John Carey , Ralph Taylor , Thomas Piazza , Jeffrey Potter , Angel Socarras
发明人： Michael Mantor , John Carey , Ralph Taylor , Thomas Piazza , Jeffrey Potter , Angel Socarras
IPC分类号： G09G5/00
CPC分类号： G09G5/39 , G06T1/60 , G06T15/04 , G09G3/003 , G09G2360/121
摘要： A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

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