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41. 发明申请

US20060095535A1 System and method for movement of non-aligned data in network buffer model 有权
标题翻译：网络缓冲模型中非对齐数据移动的系统和方法
公开(公告)号：US20060095535A1
公开(公告)日：2006-05-04
申请号：US10959801
申请日：2004-10-06
申请人： Rama Govindaraju , Chulho Kim , Hanhong Xue
发明人： Rama Govindaraju , Chulho Kim , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： H04L47/10
摘要： A method is provided for transferring data between first and second nodes of a network. Such method includes requesting first data to be transferred by a first upper layer protocol (ULP) operating on the first node of the network; and buffering second data for transfer to the second node by a lower protocol layer lower than the first ULP, the second data including an integral number of standard size units of data including the first data. The method further includes posting the second data to the network for delivery to the second node; receiving the second data at the second node; and from the received data, delivering the first data to a second ULP operating on the second node. The method is of particular application when transferring the data in unit size is faster than transferring the data in other than unit size.
摘要翻译：提供了一种用于在网络的第一和第二节点之间传送数据的方法。这种方法包括通过在网络的第一节点上操作的第一上层协议（ULP）请求首先传送的数据; 以及缓冲第二数据以通过低于所述第一ULP的较低协议层传送到所述第二节点，所述第二数据包括包括所述第一数据的标准大小数据单元的整数。该方法还包括将第二数据发布到网络以传送到第二节点; 在第二节点处接收第二数据; 并且从所接收的数据中，将第一数据传送到在第二节点上操作的第二ULP。当传输单位大小的数据比传送除单位大小之外的数据更快时，该方法是特别应用的。

42. 发明授权

US08484307B2 Host fabric interface (HFI) to perform global shared memory (GSM) operations 失效
标题翻译：主机结构接口（HFI）执行全局共享内存（GSM）操作
公开(公告)号：US08484307B2
公开(公告)日：2013-07-09
申请号：US12024397
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
IPC分类号： G06F15/167 , G06F12/00 , G06F13/00 , G06F13/28 , G06F9/46
CPC分类号： G06F12/109 , G06F9/544
摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.
摘要翻译：数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

43. 发明授权

US08275963B2 Asynchronous memory move across physical nodes with dual-sided communication 有权
标题翻译：异步存储器通过双面通信跨物理节点移动
公开(公告)号：US08275963B2
公开(公告)日：2012-09-25
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

44. 发明授权

US07958327B2 Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture 有权
标题翻译：通过在指令集体系结构中执行AMM存储指令来执行异步存储器移动（AMM）
公开(公告)号：US07958327B2
公开(公告)日：2011-06-07
申请号：US12024494
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement.
摘要翻译：具有处理器和存储器的数据处理系统包括提供异步存储器移动（AMM）存储（ST）指令的指令集架构（ISA）。当处理器执行AMM ST指令时，处理器执行一系列功能，其启动异步存储器移动（AMM）操作。 AMM ST指令通过以下方式将数据从具有第一实际地址的第一存储器位置移动到具有第二实际地址的第二存储器位置：（a）使用存储器映射的源有效地址来执行虚拟地址空间中的数据移动到第一存储器位置和存储器映射到第二存储器位置的目的地有效地址。当在虚拟地址空间中完成移动时，AMM操作将数据物理移动到处理器核心外部的第二存储器位置，而无需处理器参与。

45. 发明授权

US07941627B2 Specialized memory move barrier operations 失效
标题翻译：专业记忆移动屏障操作
公开(公告)号：US07941627B2
公开(公告)日：2011-05-10
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

46. 发明授权

US07689992B2 Sharing lock mechanism between protocol layers 失效
标题翻译：在协议层之间共享锁机制
公开(公告)号：US07689992B2
公开(公告)日：2010-03-30
申请号：US10877095
申请日：2004-06-25
申请人： Robert S. Blackmore , Su-Hsuan Huang , Chulho Kim , Richard R. Treumann , Hanhong Xue
发明人： Robert S. Blackmore , Su-Hsuan Huang , Chulho Kim , Richard R. Treumann , Hanhong Xue
IPC分类号： G06F9/46
CPC分类号： G06F9/526
摘要： Shared locks are employed for controlling a thread which extends across more than one protocol layer in a data processing system. The use of a counter is used as part of a data structure which makes it possible to implement shared locks across multiple layers. The use of shared locks avoids the processing overhead usually associated with lock acquisition and release. The thread which is controlled may be initiated in either an upper layer protocol or in a lower layer.
摘要翻译：共享锁用于控制在数据处理系统中跨越多于一个协议层延伸的线程。计数器的使用被用作数据结构的一部分，这使得可以跨多层实现共享锁。共享锁的使用避免了通常与锁获取和释放相关的处理开销。被控制的线程可以在上层协议或下层协议中启动。

47. 发明申请

US20090199200A1 Mechanisms to Order Global Shared Memory Operations 有权
标题翻译：订购全局共享内存操作的机制
公开(公告)号：US20090199200A1
公开(公告)日：2009-08-06
申请号：US12024367
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F9/50
CPC分类号： G06F12/0284 , G06F12/109 , G06F2212/656
摘要： A method and data processing system for performing fence operations within a global shared memory (GSM) environment having a local task executing on a processor and providing GSM commands for processing by a host fabric interface (HFI) window that is allocated to the task. The HFI window has one or more registers for use during local fence operations. A first register tracks a first count of task-issued GSM commands, and a second register tracks a second count of GSM operations being processed by the HFI. The processing logic detects a locally-issued fence operation, and responds by performing a series of operations, including: automatically stopping the task from issuing additional GSM commands; monitoring for completion of all the task-issued GSM commands at the HFI; and triggering a resumption of issuance of GSM commands by the task when the completion of all previous task-issued GSM commands is registered by the HFI.
摘要翻译：一种用于在全局共享存储器（GSM）环境内执行栅栏操作的方法和数据处理系统，其具有在处理器上执行的本地任务并提供用于由分配给该任务的主机结构接口（HFI）窗口进行处理的GSM命令。 HFI窗口有一个或多个寄存器用于本地栅栏操作。第一寄存器跟踪任务发出的GSM命令的第一计数，第二寄存器跟踪由HFI正在处理的GSM操作的第二计数。处理逻辑检测本地发出的围栏操作，并通过执行一系列操作进行响应，包括：自动停止任务发出附加的GSM命令; 监测在HFI完成所有任务发布的GSM命令; 并且当HFI注册所有先前任务发出的GSM命令的完成时，通过任务触发恢复发出GSM命令。

48. 发明申请

US20090198955A1 ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE) 有权
标题翻译：异常记忆移动物理名称（双面通信用于记忆移动）
公开(公告)号：US20090198955A1
公开(公告)日：2009-08-06
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

49. 发明申请

US20090198934A1 FULLY ASYNCHRONOUS MEMORY MOVER 失效
标题翻译：充分的异常记忆运动
公开(公告)号：US20090198934A1
公开(公告)日：2009-08-06
申请号：US12024613
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F12/14 , G06F9/46
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.
摘要翻译：数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。异步存储器移动器具有相关的片外转换机制。因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。

50. 发明申请

US20090198917A1 SPECIALIZED MEMORY MOVE BARRIER OPERATIONS 失效
标题翻译：专用记忆移动障碍操作
公开(公告)号：US20090198917A1
公开(公告)日：2009-08-06
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

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