专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20090144507A1 APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS 审中-公开
标题翻译：用于实现高性能存储器应用的无刷单晶振子电池的装置和方法
公开(公告)号：US20090144507A1
公开(公告)日：2009-06-04
申请号：US11950015
申请日：2007-12-04
申请人： John E. Barth, JR. , Erik L. Hedberg , Robert M. Houle , Hillery C. Hunter , Peter A. Sandon
发明人： John E. Barth, JR. , Erik L. Hedberg , Robert M. Houle , Hillery C. Hunter , Peter A. Sandon
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0891 , Y02D10/13
摘要： An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.
摘要翻译：一种用于实现无刷嵌入式动态随机存取存储器（eDRAM）高速缓存设备的装置包括具有与具有多个高速缓存线的DRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效的位和对应于所述多个高速缓存行中的每一条的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，所述定义的评估周期小于DRAM数据高速缓存中的数据的保留时间。对于在定义的评估周期期间未被访问的任何高速缓存行，将与其相关联的单个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。

42. 发明申请

US20090144504A1 STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS 审中-公开
标题翻译：用于实现高性能存储器应用的无刷单晶片单元的结构
公开(公告)号：US20090144504A1
公开(公告)日：2009-06-04
申请号：US12116234
申请日：2008-05-07
申请人： John E. Barth, JR. , Erik L. Hedberg , Robert M. Houle , Hillery C. Hunter , Peter A. Sandon
发明人： John E. Barth, JR. , Erik L. Hedberg , Robert M. Houle , Hillery C. Hunter , Peter A. Sandon
IPC分类号： G06F12/00
CPC分类号： G06F12/0893
摘要： A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有与包括多个高速缓存线的eDRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效位和对应于所述多个高速缓存行中的每一个的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，其小于DRAM数据高速缓存中的数据的保留时间; 其中，对于在定义的评估周期期间作为读取或写入操作的结果未被访问的任何高速缓存行，将与其相关联的各个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。

43. 发明申请

US20090094566A1 DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM 审中-公开
标题翻译：芯片识别系统设计结构
公开(公告)号：US20090094566A1
公开(公告)日：2009-04-09
申请号：US12105883
申请日：2008-04-18
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06K19/067
摘要： Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了用于片上识别电路的设计结构。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

44. 发明申请

US20090091351A1 CHIP IDENTIFICATION SYSTEM AND METHOD 有权
标题翻译：芯片识别系统和方法
公开(公告)号：US20090091351A1
公开(公告)日：2009-04-09
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： H03K19/00 , H01L23/544
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

45. 发明申请

US20080282072A1 Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table 审中-公开
标题翻译：使用功能可编程分支表在实时硬件约束中执行软件
公开(公告)号：US20080282072A1
公开(公告)日：2008-11-13
申请号：US11745657
申请日：2007-05-08
申请人： Todd E. Leonard , Jason M. Norman , Peter A. Sandon
发明人： Todd E. Leonard , Jason M. Norman , Peter A. Sandon
IPC分类号： G06F9/44 , G06F15/00 , G06F9/46
CPC分类号： G06F9/30054 , G06F15/7867
摘要： A computer system is disclosed which includes a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received.
摘要翻译：公开了一种计算机系统，其包括用于驱动紧密约束的硬件事件的CPU或微处理器。该系统包括具有用于驱动功能可编程事件的一组系统输入的处理器，以及CPU中的快速分支，包括状态处理程序，以执行来自CPU的处理该事件的指令。 CPU中的队列存储事件，使得非预先占用的事件按照接收的顺序进行服务。

46. 发明授权

US07386703B2 Two dimensional addressing of a matrix-vector register array 有权
标题翻译：矩阵向量寄存器阵列的二维寻址
公开(公告)号：US07386703B2
公开(公告)日：2008-06-10
申请号：US10715688
申请日：2003-11-18
申请人： Peter A. Sandon , R. Michael P. West
发明人： Peter A. Sandon , R. Michael P. West
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧1, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：一种用于处理矩阵数据的处理器和方法。处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N> = 2，M> = 2，K> = 1，B> = 1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

47. 发明授权

US6112300A Method and apparatus for performing multi-way branching using a hardware relational table 失效
标题翻译：使用硬件关系表执行多路分支的方法和装置
公开(公告)号：US6112300A
公开(公告)日：2000-08-29
申请号：US89973
申请日：1998-06-03
申请人： Thomas E. Cook , Yu-Chung C. Liao , Peter A. Sandon
发明人： Thomas E. Cook , Yu-Chung C. Liao , Peter A. Sandon
IPC分类号： G06F9/312 , G06F9/32 , G06F9/345
CPC分类号： G06F9/30043 , G06F9/30058
摘要： Multi-way branching is implemented via a single instruction by providing a computer system with a hardware token-to-address table, loading the table with branch target data correlating to the multi-way branch instruction, including software for execution with at least one multi-way branch instruction executing that branch instruction by accessing the table. The computer system is conventionally supplied with branch logic and general purpose register stack with a multi-ported output interface. The hardware resource added implementing the multi-way branch operation includes the table in the form of addressable storage comprising a plurality of multi-byte locations with a write data input and a read data output. A decoder is connected between one port of the general purpose register interface with an output to select one of the multi-byte locations for an input or output operation. The write data input of the addressable storage or table is connected to another port of the general purpose register interface. The read data output of the addressable storage is connected to the branch logic so that data may be written from a port of the general purpose registers to a location in the addressable storage determined by an associated index obtained from another port of the general purpose register and data may be selected for output from the addressable storage to the branch logic by applying an index from a port of the general purpose registers to effect a data read operation.
摘要翻译：通过向计算机系统提供硬件令牌到地址表来实现多路分支，通过与多路分支指令相关联的转移目标数据加载表，其中包括与至少一个多个执行的执行的软件 -way分支指令通过访问表执行该分支指令。计算机系统通常具有分支逻辑和具有多端口输出接口的通用寄存器堆栈。添加实现多路分支操作的硬件资源包括可寻址存储器形式的表，其中包括具有写数据输入和读数据输出的多个多字节位置。解码器连接在通用寄存器接口的一个端口与输出端之间，以选择输入或输出操作的多字节位置之一。可寻址存储器或表的写入数据输入连接到通用寄存器接口的另一个端口。可寻址存储器的读取数据输出连接到分支逻辑，使得数据可以从通用寄存器的端口被写入可寻址存储器中由通用目的寄存器的另一个端口获得的关联索引确定的位置，可以通过从通用寄存器的端口应用索引来选择数据以从可寻址存储器到分支逻辑的输出，以进行数据读取操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式