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41. 发明授权

US06581115B1 Data processing system with configurable memory bus and scalability ports 有权
标题翻译：具有可配置内存总线和可扩展端口的数据处理系统
公开(公告)号：US06581115B1
公开(公告)日：2003-06-17
申请号：US09436423
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , James Steven Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , James Steven Fields, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： A data processing system with configurable processor chip buses. The processor chip is designed with a plurality of extended buses of which a number are configurable buses (i.e., capable of being allocated to one of several external components, particularly memory and other SMPs). The processor chip allows for the static allocation of these configurable buses to these external components, based primarily on vendor system design preferences.
摘要翻译：具有可配置处理器芯片总线的数据处理系统。处理器芯片设计有多个扩展总线，其中数字是可配置总线（即，能够被分配给几个外部组件中的一个，特别是存储器和其他SMP）。处理器芯片允许将这些可配置总线静态分配到这些外部组件，主要基于供应商系统设计偏好。

42. 发明授权

US06374333B1 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention 失效
标题翻译：缓存一致性协议，其中使用加载指令提示位来指示由干预提供的修改的高速缓存行的释放
公开(公告)号：US06374333B1
公开(公告)日：2002-04-16
申请号：US09437176
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

43. 发明授权

US06345343B1 Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state 有权
标题翻译：多处理器总线协议，包括读取请求，其具有在提供所请求的修改值时具有指定解除分配的襟翼
公开(公告)号：US06345343B1
公开(公告)日：2002-02-05
申请号：US09437178
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

44. 发明授权

US08122132B2 Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
标题翻译：基于广播信息将作业动态地分配给集群中的处理器的技术
公开(公告)号：US08122132B2
公开(公告)日：2012-02-21
申请号：US12336312
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F13/00
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).
摘要翻译：用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息多个节点中的一个。基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

45. 发明申请

US20100153541A1 TECHNIQUES FOR DYNAMICALLY ASSIGNING JOBS TO PROCESSORS IN A CLUSTER BASED ON PROCESSOR WORKLOAD 有权
标题翻译：基于处理器工作负载的集群中的处理器动态组织工作的技术
公开(公告)号：US20100153541A1
公开(公告)日：2010-06-17
申请号：US12336256
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F15/173
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.
摘要翻译：用于操作高性能计算（HPC）集群的技术包括监视包含在HPC集群中的多个处理器的工作负载。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。基于多个处理器的工作负载，分配给多个处理器中的一个或多个的一个或多个线程被移动到多个处理器中的不同处理器。

46. 发明授权

US06629209B1 Cache coherency protocol permitting sharing of a locked data granule 失效
标题翻译：缓存一致性协议允许共享锁定的数据粒子
公开(公告)号：US06629209B1
公开(公告)日：2003-09-30
申请号：US09437185
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

47. 发明授权

US06625701B1 Extended cache coherency protocol with a modified store instruction lock release indicator 失效
标题翻译：扩展缓存一致性协议，具有修改后的存储指令锁定释放指示器
公开(公告)号：US06625701B1
公开(公告)日：2003-09-23
申请号：US09437183
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1214
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

48. 发明授权

US06535939B1 Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations 失效
标题翻译：通过硬件监控的总线利用率，可动态配置的内存总线和可扩展端口
公开(公告)号：US06535939B1
公开(公告)日：2003-03-18
申请号：US09436418
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , James Steven Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , James Steven Fields, Jr.
IPC分类号： G06F1314
CPC分类号： G06F13/36
摘要： A data processing system with configurable processor chip buses. The processor chip is designed with a bus allocation unit and has a plurality of extended buses of which a number are configurable buses (i.e. may be dynamically allocated to any one of several external components, particularly memory and other SMPs). A priority determination of bandwidth requirements of the external components is made during system processing. Then the configurable buses are dynamically allocated to the external components based on their bandwidth requirement and/or the configuration which provides the best overall system efficiency.
摘要翻译：具有可配置处理器芯片总线的数据处理系统。处理器芯片设计有总线分配单元，并且具有多个扩展总线，其中数字是可配置总线（即可以动态地分配给多个外部组件中的任何一个，特别是存储器和其他SMP）。在系统处理期间，对外部组件的带宽需求进行优先确定。然后，可配置总线根据其带宽要求和/或提供最佳整体系统效率的配置动态地分配给外部组件。

49. 发明授权

US06345342B1 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line 有权
标题翻译：缓存一致性协议采用包括可编程标志的读取操作来指示干预的高速缓存行的解除分配
公开(公告)号：US06345342B1
公开(公告)日：2002-02-05
申请号：US09437177
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（Mu）高速缓存状态，以指示保持在高速缓存行中的值已经被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用Mu状态。读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

50. 发明授权

US06321306B1 High performance multiprocessor system with modified-unsolicited cache state 失效
标题翻译：具有修改的主动缓存状态的高性能多处理器系统
公开(公告)号：US06321306B1
公开(公告)日：2001-11-20
申请号：US09437179
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1212
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

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